Amplifiers – With semiconductor amplifying device – Including signal feedback means
Reexamination Certificate
2000-03-31
2001-10-23
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including signal feedback means
Reexamination Certificate
active
06307437
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to active loads in linear analog circuits generally and, more particularly, to pole spreading of active loads in linear analog circuits.
BACKGROUND OF THE INVENTION
Conventional linear analog circuits, such as two stage amplifiers, implement an active load stage. Conventional active load stages have (i) large DC and low frequency gains and (ii) a dominant pole resulting from a high output impedance and large parasitic capacitance at a respective output node. The gain of conventional amplifiers will remain above one at a frequency when the combined phase shift of the inverting amplifier, a dominant pole and the higher order poles equal 360 degrees. Conventional amplifiers require an additional capacitance at the dominant pole node to shift the dominant pole to an even lower frequency causing the gain to be below one when the total phase shift equals 360 degrees.
Conventional amplifiers implement an additional resistor to increase the phase margin of the amplifier by placing a zero on the next higher order pole. The resistor can be added in series with the capacitor to create a zero at the next higher order pole. However, a parasitic capacitance at the output node will eventually create another pole. The additional pole will cause the phase shift to again approach 360 degrees before the loop gain drops below one. The parasitic capacitance limits gain bandwidth (GBW) of conventional amplifiers.
Active loads are common in conventional amplifiers. The active loads are common because of (i) large dynamic output impedances for relatively high currents and (ii) simplistic conventional architecture. Active loads at high frequencies have large parasitic capacitances which can negate gain advantages of the high dynamic impedance of the active load at low frequencies. Conventional amplifiers may cause a dominant pole to be generated at 1/[(2&pgr;Ro)(Cdw+Cpar)], where Cdw is a drain to well capacitance, Cpar is a parasitic capacitance and Ro is a dynamic output resistance of the active load in parallel with the impedance of an output transistor. The dominant pole is required to be shifted to a lower frequency. The dominant pole is required to be shifted so the gain will fall below one before the total phase shift exceeds 360 degrees.
It is desirable to implement a method and/or architecture that may present an open loop gain that is less than one at a frequency lower that the frequency at which the total phase shift exceeds 360 degrees.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising an analog circuit, a passive circuit and a first circuit. The analog circuit may be configured to vary a voltage of an output signal in response to a first signal. The passive circuit may be configured to further vary the voltage. The first circuit may be configured to further vary the voltage. The first circuit generally comprises a parasitic capacitance. The passive circuit and the first circuit are generally coupled in series.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) eliminate (or reduce) the effect of the drain to well capacitance, (ii) provide an increased gain bandwidth, (iii) reduce a size of a compensation capacitor and/or (iv) prevent a parasitic capacitance of a load from creating an additional pole at a node.
REFERENCES:
patent: 5392000 (1995-02-01), Gillig
patent: 5420542 (1995-05-01), Harvey
Henrion W. S.
Kruczkowski Phillip
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Mottola Steven J.
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