MOS interchip receiver differential amplifiers employing resisto

Details MOS interchip receiver differential amplifiers employing resisto MOS interchip receiver differential amplifiers employing resisto

1976-06-30

1978-02-14

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307205, 307251, 307304, 307DIG3, 330277, 330253, H03K 520, H03K 1704, H03K 1760, H03K 1908

Patent

active

040741508

ABSTRACT:
A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor, to which this application is directed to, as the shunt feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.

REFERENCES:
patent: 3392341 (1968-07-01), Burns
patent: 3676702 (1972-07-01), McGrogan, Jr.
patent: 3855549 (1974-12-01), Heuner et al.
patent: 3870966 (1975-03-01), Dingwall
patent: 3886464 (1975-05-01), Dingwall
patent: 3904988 (1975-09-01), Hsiao
patent: 3943380 (1976-03-01), Morgan et al.
patent: 3956643 (1976-05-01), Hite
patent: 3956708 (1976-05-01), Musa

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