MOS integrated circuit device operating with low power...

Details MOS integrated circuit device operating with low power... MOS integrated circuit device operating with low power...

2000-05-25

2001-12-25

Ballato, Josie (Department: 2836)

Electrical transmission or interconnection systems

Switching systems

Condition responsive

C307S115000, C327S534000, C327S537000, C327S544000

Reexamination Certificate

active

06333571

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device which includes an MOS transistor (insulated gate type field effect transistor) as a component. More particularly, the present invention relates to a structure for achieving the low power consumption and high speed operation of an MOS semiconductor integrated circuit device which can operate in a plurality of operation modes.
2. Description of the Background Art
FIG. 19
shows an example of the structure of a conventional semiconductor integrated circuit device disclosed in Japanese Patent Laying-Open No. 6-291267, for example.
In
FIG. 19
, the conventional semiconductor integrated circuit device includes CMOS inverters IVa, IVb, IVc and IVd of four stages cascaded between an input node
101
and an output node
102
. Each of CMOS inverters IVa-IVd operates using a power supply voltage VDD applied on a power supply node and a ground voltage GND applied on a ground node as one and another operational power supply voltages. Each of the inverters inverts an applied signal for output.
CMOS inverters IVa-IVd include respective P channel MOS transistors Pa-Pd for outputting an H level signal and respective N channel MOS transistors Na-Nd for outputting an L level signal.
The semiconductor integrated circuit device further includes a first voltage generation circuit
110
a
commonly connected to the substrate regions (back gates) of P channel MOS transistors Pa-Pd and outputting a back gate voltage Vps in accordance with a control signal from a control circuit
112
a
, and a second voltage generation circuit
110
b
commonly connected to the substrate regions (back gates) of N channel MOS transistors Na-Nd and outputting a back gate voltage Vns in accordance with a control signal from a control circuit
112
b
. The operation will briefly be described below.
Now, consider the case in which output voltage Vps from first voltage generation circuit
110
a
is set to a voltage level which is slightly lower than power supply voltage VDD in accordance with the control signal from control circuit
112
a
, and output voltage Vns from second voltage generation circuit
110
b
is set to a voltage level which is slightly higher than ground voltage GND in accordance with the control signal from control circuit
112
b.
In this case, when an input signal applied to input node
101
makes a transition from an L level to an H level, an output signal applied to output node
102
through CMOS inverters IVa-IVd of four stages makes a transition from the L level to the H level. When back gate voltage Vps of P channel MOS transistors Pa-Pd is lower than power supply voltage VDD, depletion layers in the channel formation regions of P channel MOS transistors Pa-Pd are widened. In N channel MOS transistors Na-Nd as well, when back gate voltage Vns is higher than ground voltage GND, depletion layers are wider than when ground voltage GND is applied to the back gates. Therefore, when P channel MOS transistors Pa-Pd and N channel MOS transistors Na-Nd are switched on and rendered conductive to form the channels, the widened depletion layers increase the channel sectional areas and the amount of moving carriers. Accordingly, MOS transistors Pa-Pd and Na-Nd are switched on and off at high speed, and the amount of drive current and the response speed are increased.
Even when the input signal applied to input node
101
makes a transition from the H level to the L level, MOS transistors Pa-Pd and Na-Nd are operated at high speed due to back gate voltages Vps and Vns, and the signal of output node
102
makes a transition from the H level to the L level.
Now, consider the case in which back gate voltage Vps from first voltage generation circuit
110
a
is set to a voltage level higher than power supply voltage VDD in accordance with the control signal from control circuit
112
a
, and back gate voltage Vns from second voltage generation circuit
110
b
is set to a voltage level lower than ground voltage GND in accordance with the control signal from control circuit
112
b.
In this case, the depletion layers of MOS transistors Pa-Pd and Na-Nd become narrower than when power supply voltage VDD and ground voltage GND are applied as the back gate voltages, and channel formation is suppressed. In this case, when the signal applied to input node
101
makes a transition from the L level to the H level, CMOS inverters IVa-IVd cause the output signal at output node
102
to make a transition from the L level to the H level. However, since the depletion layers are narrower and the channel sectional areas are accordingly smaller, the amount of moving carriers, the amount of current and the response speed are reduced.
Therefore, by adjusting the voltage levels of back gate voltages Vps and Vns output from voltage generation circuits
110
a
and
110
b
, the amount of drive current and the response speed of a semiconductor circuit can be adjusted depending on applications.
In order to reduce the response time to allow the high speed operation in the semiconductor integrated circuit device shown in
FIG. 19
, voltage Vps applied to the back gates of P channel MOS transistors Pa-Pd is set to the voltage level of Vps
1
slightly lower than power supply voltage VDD, and voltage Vns applied to the back gates of N channel MOS transistors Na-Nd is set to the voltage level of Vns
1
slightly higher than ground voltage GND, as shown in FIG.
20
. Thus, the back gate biases of MOS transistors Pa-Pd and Na-Nd are made slightly shallower and the depletion layers formed immediately under the channels are slightly widened. On the other hand, for the low speed operation, back gate voltage Vps is set to the voltage level of Vps
2
slightly higher than power supply voltage VDD, and back gate voltage Vns of N channel MOS transistors Na-Nd is set to a voltage level slightly lower than ground voltage GND. Thus, the back gate biases of MOS transistors Pa-Pd and Na-Nd are made deeper, the depletion layers are made narrower, and the amount of drive current is reduced.
Back gate voltages Vps and Vns each determine the threshold voltage of an MOS transistor, and the threshold voltages of MOS transistors Pa-Pd and Na-Nd are changed according to the values of back gate voltages Vps and Vns. On the other hand, a current called a subthreshold leakage current is known in an MOS transistor.
FIG. 21
shows the relationship between a gate-to-source voltage Vgs and a drain current Ids in the subthreshold region of an N channel MOS transistor. In
FIG. 21
, the ordinate indicates drain current Ids in a logarithm scale and the abscissa indicates gate-to-source voltage Vgs. The threshold voltage of an MOS transistor is defined as a gate-to-source voltage causing a prescribed drain current to flow in an MOS transistor having a predetermined gate width. In
FIG. 21
, a curve I indicates gate-to-source voltage Vgs and drain current Ids when the threshold voltage is Vth
1
, while a curve II indicates the relationship between drain current Ids and gate-to-source voltage Vgs of an MOS transistor having a threshold voltage Vth
2
. A region in which curves I and II change linearly is where drain current Ids decreases exponentially, and it is called a subthreshold region.
As shown in
FIG. 21
, a current of a certain magnitude flows in an MOS transistor even if gate-to-source voltage Vgs is 0V. Usually, this current is called a subthreshold leakage current. As the threshold voltage increases, the subthreshold leakage current decreases. However, the operation speed of an MOS transistor is lowered as the threshold voltage increases. If the back gate bias is made deeper (shifted in a negative direction) in an N channel MOS transistor, the threshold voltage is increased and the characteristic curve changes from curve I to curve II as shown in FIG.
21
. The relationship between the drain current and the gate-to-source voltage of a P channel MOS transistor is obtained by inverting the sign of gate-to-source voltage Vgs of the graph shown in FIG.
2

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