MOS Integrated circuit

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Details

357 41, 357 86, 357 89, H01L 2704

Patent

active

043181171

ABSTRACT:
A MOS integrated circuit including P-channel MOS transistors, particularly for C-MOS inverter, in which the P-channel MOS transistor (12) has P.sup.+ drain (34), P.sup.+ source (36) connected to a +VDD circuit (42) via P.sup.+ and N.sup.+ diffusion layers (36.sub.1, 36.sub.2) and isolation gate (38). The P.sup.+ layer is partly replaced by, i.e. parallel- and/or serial-connected to the N.sup.+ layer so that an effective source diffusion resistance (R.sub.S) or the conductive resistance (R.sub.0) is lowered.

REFERENCES:
RCA COS/MOS IC's Manual, Tech. Series CMS-270, (RCA, Somerville, N.J., 1971) pp. 24-26.

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