1979-11-13
1982-03-02
Larkins, William D.
357 41, 357 86, 357 89, H01L 2704
Patent
active
043181171
ABSTRACT:
A MOS integrated circuit including P-channel MOS transistors, particularly for C-MOS inverter, in which the P-channel MOS transistor (12) has P.sup.+ drain (34), P.sup.+ source (36) connected to a +VDD circuit (42) via P.sup.+ and N.sup.+ diffusion layers (36.sub.1, 36.sub.2) and isolation gate (38). The P.sup.+ layer is partly replaced by, i.e. parallel- and/or serial-connected to the N.sup.+ layer so that an effective source diffusion resistance (R.sub.S) or the conductive resistance (R.sub.0) is lowered.
REFERENCES:
RCA COS/MOS IC's Manual, Tech. Series CMS-270, (RCA, Somerville, N.J., 1971) pp. 24-26.
Osanai Hiroshi
Satoh Yasushi
Suzuki Yasoji
Takada Minoru
Larkins William D.
Tokyo Shibaura Denki Kabushiki Kaisha
LandOfFree
MOS Integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS Integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS Integrated circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-62008