MOS Input circuit with selectable stabilized trip voltage

Details MOS Input circuit with selectable stabilized trip voltage MOS Input circuit with selectable stabilized trip voltage

1978-08-10

1980-12-30

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307290, 307DIG1, H03K 17687, H03K 1714, H03K 19092, H03K 3356

Patent

active

042426049

ABSTRACT:
Disclosed is an integrated buffer circuit having a selectable stabilized trip voltage. The circuit includes an input stage and a reference stage. Each of these stages includes an MOS field effect transistor, a substantially constant resistance device coupling the drain of the input transistor to a bias source, and a device having a resistance that is variable in response to control signals coupling the source of the input transistor to another bias source. The reference stage is biased in the linear region at the selectable trip voltage. A signal generated at the drain of the transistor in the reference stage is connected to all of the variable resistance devices as the control signal. This signal varies the variable resistance in such a way as to compensate for threshold voltage variations in the transistor of the input stage and thus stabilize the selected trip voltage of the input stage.

REFERENCES:
patent: 3581120 (1971-05-01), Nord
patent: 3873856 (1975-03-01), Gerlach et al.
patent: 4064468 (1977-12-01), Kumata
patent: 4110641 (1978-08-01), Payne
Frantz, "Threshold Voltage Control for N-Channel MOSFET Devices", IBM Tech. Discl. Bull., vol. 12, No. 12, 5/1970.

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