MOS I/O protection using switched body circuit design

Details MOS I/O protection using switched body circuit design MOS I/O protection using switched body circuit design

1987-08-31

1988-12-06

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

357 2313, 361 92, H02H 324

Patent

active

047899174

ABSTRACT:
Switched body circuitry is provided to prevent a system I/O from being effected by the loss of power supply or ground to an MOS integrated circuit within the system. A semiconductor substrate of a first conductivity type has formed therein a well region of a second conductivity type opposite to that of the first conductivity type. First, second, third and fourth spaced-apart shallow diffusion regions of the first conductivity type are formed at the surface of the well region. A first gate electrode and the second and third diffusion regions combine to form an MOS transistor which is either an input pull up or pull down device or an output pull up or pull down driver of the MOS circuit. A second gate electrode and the third and fourth diffusion regions combine to define a first MOS switched body transistor. A third gate electrode and the first and second diffusion regions combine to define a second MOS switched body transistor. These two transistors control the potential of the I/O transistor's body (P-well or N-well) so as to keep the parasitic and ESD protection bipolar transistors and diode turned off during loss of power or ground to the chip.

REFERENCES:
patent: 4066918 (1978-01-01), Heuner et al.
patent: 4213140 (1980-07-01), Okabe et al.
patent: 4255671 (1981-03-01), Nonaka et al.
patent: 4303958 (1981-12-01), Allgood

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