Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1999-09-22
2003-05-06
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S401000, C257S618000, C257S623000, C257S628000, C438S287000, C438S496000, C438S502000
Reexamination Certificate
active
06559518
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to MOS heterostructure, semiconductor device with such a structure, and method for fabricating the semiconductor device.
An MOS field effect transistor (MOSFET) with a metalinsulator-semiconductor structure is well known in the art as a typical field effect transistor. The MOSFET is called as such because an oxide is regarded as a representative insulator of the structure. Thus, in this specification, such a structure including any of various types of insulators will be collectively called an “MOS heterostructure”.
Hereinafter, a conventional method for fabricating an MOSFET will be described with reference to FIGS.
9
(
a
) through
9
(
d
).
First, as shown in FIG.
9
(
a
), an ordinary silicon substrate
50
, i.e., a semiconductor substrate of single crystal silicon, is prepared. Then, as shown in FIG.
9
(
b
), a silicon oxide film
51
is formed thereon by thermally oxidizing the surface of the silicon substrate
50
. The silicon oxide film
51
is mainly composed of amorphous silicon dioxide (SiO
2
).
Next, a conductive thin film (not shown) such as a polysilicon film is deposited on the silicon oxide film
51
. A resist pattern (not shown) is defined thereon to cover part of the conductive thin film in which a gate electrode should be formed. Then, the conductive thin film and silicon oxide film
51
are etched in this order using the resist pattern as a mask. In this manner, a gate insulating film
52
and a gate electrode
53
are formed out of the silicon oxide film
51
and conductive thin film, respectively, in this order on the silicon substrate
50
as shown in FIG.
9
(
c
).
Thereafter, as shown in FIG.
9
(
d
), a sidewall oxide film
54
is formed on the side faces of the gate electrode
53
. And the silicon substrate
50
is doped with a dopant using the gate electrode
53
and sidewall oxide film
54
as a mask, thereby forming source/drain regions
55
and
56
in the substrate
50
. In this case, when a predetermined voltage is applied between the silicon substrate
50
and gate electrode
53
, a channel
57
is formed within a region of the silicon substrate
50
in the vicinity of the interface between the substrate
50
and gate insulating film
52
.
In the conventional process, however, some strain is caused in the interface between the silicon substrate
50
and silicon oxide film
51
(hereinafter, called “silicon/thermal oxide interface”) while the surface of the substrate
50
is being thermally oxidized to form the silicon oxide film
51
to be the gate insulating film
52
thereon. This is because the silicon oxide film
51
goes on expanding as the film
51
is growing on the surface of the silicon substrate
50
. Accordingly, various structural defects are developed within the silicon substrate
50
, thereby possibly creating interface states. These interface states in turn form carrier-trapping sites to cause the dielectric breakdown of the gate insulating film
52
or considerably decrease the mobility of carriers in the channel
57
. As a result, the performance of the MOSFET deteriorates and therefore the transistor cannot operate at high speeds anymore.
FIG.
10
(
a
) illustrates a schematic partial cross section of an MOSFET fabricated by the conventional method near the silicon/thermal oxide interface, while FIG.
10
(
b
) illustrates respective energy levels of the conduction and valence bands near the silicon/thermal oxide interface.
According to the conventional method for fabricating an MOSFET, while the silicon oxide film
51
is being formed within a surface region of the silicon substrate
50
, part of the surface region is not oxidized completely. As a result, a structural transition layer
51
a
, which is a silicon suboxide (SiO
x
, where x≦about 1.7) layer as thin as about 0.2 to about 0.3 nm, is formed as a part of the silicon oxide film
51
in the vicinity of the interface between the film
51
and silicon substrate
50
as shown in FIG.
10
(
a
). An ordinary amorphous SiO
2
layer
51
b
with a thickness of several nanometers is formed on the structural transition layer
51
a
. The SiO
x
structural transition layer
51
a
relaxes a strain caused between the Si substrate
50
and SiO
2
layer
51
b
. However, the chemical bonds in the structural transition layer
51
a
are easily broken by electrons traveling in the channel
57
. In other words, since the structural transition layer
51
a
is easily broken by the intrusion of electrons, i.e., channel hot electrons, the structural transition layer
51
a
is electrically unstable.
Also, as shown in FIG.
10
(
b
), the respective energy levels e
1
and e
2
at the conduction and valence bands are bent in a wide region, including the structural transition layer
51
a
, within the silicon oxide film
51
, i.e., in the gate insulating film
52
. Hereinafter, such a phenomenon will be called “bending”. Because of this bending, the band gap of the silicon oxide film
51
considerably decreases vertically downward, i.e., toward the silicon/thermal oxide interface. As a result, the breakdown voltage and reliability of the silicon oxide film
51
, i.e., the gate insulating film
52
, both greatly decline.
In addition, the thinner that part of the silicon oxide film
51
to be the gate insulating film
52
(i.e., the SiO
2
layer
51
b
), the higher percentage of the silicon oxide film
51
the structural transition layer
51
a
accounts for. Thus, the thicker the structural transition layer
51
a
is getting, the more seriously the performance of the transistor is affected by the structural defects in the silicon/thermal oxide interface.
Specifically, the structural transition layer
51
a
is about 0.2 to about 0.3 nm thick and that part of the silicon oxide film
51
with a decreased band gap is as thick as about 1 nm. Even if the thickness of the silicon oxide film
51
is reduced, however, the thickness of the structural transition layer
51
a
remains almost the same. Accordingly, if the thickness of the silicon oxide film
51
is reduced, then the structural transition layer
51
a
accounts for the increased percentage of the silicon oxide film
51
. In addition, a larger proportion of the silicon oxide film
51
comes to have a smaller band gap. As a result, the silicon oxide film
51
, i.e., the gate insulating film
52
, has its breakdown voltage further decreased.
Furthermore, as the structural transition layer
51
a
accounts for an increasing percentage of the silicon oxide film
51
, then the thickness of the silicon oxide film
51
becomes non-uniform or the silicon/thermal oxide interface is roughened. In such a case, the electrons in the channel
57
travel along the silicon/thermal oxide interface while being affected by the roughened interface. As a result, the probability of electron scattering increases. Moreover, as a field effect transistor is downsized, the effective vertical field intensity, which is the intensity of an electric field vertical to the silicon/thermal oxide interface, rises, thus making the electron scattering phenomenon even more significant. Accordingly, if the gate insulating film
52
is thinned to downsize an MOSFET, then the mobility of electrons in the channel
57
, or the transconductance, decreases, thereby interfering with the performance enhancement of the MOSFET.
SUMMARY OF THE INVENTION
A first, general object of the present invention is providing an MOS heterostructure with reduced structural defects in a semiconductor substrate.
A second, more specific object of the present invention is providing an MOS heterostructure where no structural transition layer exists within a region of an insulating film on a semiconductor substrate in the vicinity of the interface between the insulating film and the substrate.
To achieve the first object, an MOS heterostructure according to the present invention includes: a single crystal silicon substrate; an insulating film formed on the substrate; and a conductive film formed on the insulating film. The substrate includes a plurality of te
Kang Donghee
Loke Steven
Nixon & Peabody LLP
Studebaker Donald R.
LandOfFree
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