MOS full adder circuit

Details MOS full adder circuit MOS full adder circuit

1983-09-30

1986-04-15

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

045831920

ABSTRACT:
An MOS full adder circuit having a sum circuit portion and a carry circuit portion is provided. In an embodiment utilizing transistors of opposite conductivity type, both the sum and carry circuits are symmetrical, thereby simplifying the physical layout of the full adder during fabrication.

REFERENCES:
patent: 3766371 (1973-10-01), Suzuki
patent: 4071905 (1978-01-01), Oguchi et al.
patent: 4417314 (1983-11-01), Best
patent: 4471454 (1984-09-01), Dearden et al.
patent: 4523292 (1985-06-01), Armer
Varadarajan, "Full Binary Adder Employing Fewer Components", IBM Technical Disclosure Bulletin, vol. 18, No. 9, Feb. 1976, p. 2880.
Mano, Digital Logic and Computer Design, Prentice-Hall, Inc., 1979, pp. 119-123.

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