MOS four-quadrant multiplier including the voltage-controlled-th

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

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Details

327357, 327358, 327359, 327560, G06G 716

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active

057740100

ABSTRACT:
A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. Each of the first and second two-quadrant multipliers has first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains not cross-coupled to drains of the third pair of transistors, the second pair of transistors has gates connected to drains of the first pair of transistors, respectively, and the third pair of transistors has gates connected in common to each other at a node. The differential output current of each two-quadrant multiplier contains at least a drain current of the second pair of transistors. The differential outputs of the both two-quadrant multipliers are cross-coupled to each other to output a combined differential output current. The first differential input voltage is applied between the gates of the first pair of transistors, and the second differential input voltage is applied between the node of the first two-quadrant multiplier and the node of the second two-quadrant multiplier.

REFERENCES:
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patent: 5151625 (1992-09-01), Zarabadi et al.
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patent: 5578965 (1996-11-01), Kimura
patent: 5581210 (1996-12-01), Kimura
K. Bult et al., "A CMOS Four-Quadrant Analog Multiplier," IEEE Journal of Solid-State Circuits, vol. SC-21, No. 3, Jun. 1986, pp. 338, 339, 344, 345, 478, and 479.
K. Kimura, "An MOS Four-Quadrant Analog Multiplier Based on the Multitail Technique Using a Quadritail Cell as a Multiplier Core," IEEE Transactions on Circuits and Systems --1:Fundamental Theory and Applications, vol. 42, No. 8, Aug. 1995, pp. 449-454.

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