MOS four-quadrant multiplier including the voltage-controlled-th

Details MOS four-quadrant multiplier including the voltage-controlled-th MOS four-quadrant multiplier including the voltage-controlled-th

1997-05-16

1998-10-20

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327359, 327560, 327563, G06F 744

Patent

active

058252320

ABSTRACT:
A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. The combined differential output current includes a plurality of differential output currents. First and second two-quadrant multipliers included in the MOS four-quadrant multiplier each have first and second pairs of transistors including sources connected in common to each other. A third pair of transistors is connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains which are not connected in common to drains of the third pair of transistors. The second pair of transistors has gates respectively connected to drains of said first pair of transistors and sources of said third pair of transistors. The third pair of transistors of each of the first and second two-quadrant multipliers have gates connected in common to each other at a node. Each differential output current generated in a corresponding one of the first and second two-quadrant multipliers includes at least a drain current of the second pair of transistors. The differential outputs of the first and second two-quadrant multipliers are connected to each other to output the combined differential output current. The first differential input voltage is applied between the gates of the first pair of transistors, and the second differential input voltage is applied between the node of the first two-quadrant multiplier and the node of the second two-quadrant multiplier.

REFERENCES:
patent: 3689752 (1972-09-01), Gilbert
patent: 5151625 (1992-09-01), Zarabadi et al.
patent: 5187682 (1993-02-01), Kimural
patent: 5396131 (1995-03-01), Miki et al.
patent: 5438296 (1995-08-01), Kimura
patent: 5448772 (1995-09-01), Granfield
"A CMOS Four-Quadrant Analog Multiplier", K. Bult and H. Wallinga, IEEE Journal of Solid State Circuits, vol. SC-21, No. 3, Jun. 1986, pp. 430-435 .

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