MOS floating gate memory cell containing tunneling diffusion reg

Details MOS floating gate memory cell containing tunneling diffusion reg MOS floating gate memory cell containing tunneling diffusion reg

1987-07-16

1989-04-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437043, H01L 2704, H01L 2713

Patent

active

048227501

ABSTRACT:
A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.

REFERENCES:
patent: 4203158 (1980-05-01), Frohman et al.
patent: 4426764 (1984-01-01), Kosa et al.
patent: 4532535 (1985-07-01), Gerber et al.

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