MOS floating gate memory cell and process for fabricating same

Details MOS floating gate memory cell and process for fabricating same MOS floating gate memory cell and process for fabricating same

1986-12-01

1987-10-20

Larkins, William D.

357 2311, 357 42, 357 89, H01L 2710, H01L 2978, G11C 1140

Patent

active

047017767

ABSTRACT:
A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.

REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky
patent: 4451904 (1984-05-01), Sugiura
patent: 4460979 (1984-07-01), Brahmbhatt
patent: 4477825 (1984-10-01), Yaron et al.
patent: 4532535 (1985-07-01), Gerber et al.

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