1988-03-07
1990-01-09
Laroche, Eugene R.
357 20, 357 233, H01L 2978, H01L 2906
Patent
active
048931560
ABSTRACT:
The disclosed MOS FET device has a semiconductor substrate of for instance n-type, on which a drain zone of for instance p-type and a source zone of for instance p-type are formed with a channel zone disposed therebetween. An insulating thin film is disposed on the channel zone and a gate electrode is formed on the insulating film so as to face the channel zone across the film. At least one of drain zone and the source zone has a tapered portion whose diminished edge extends into the channel zone so as to face the other one of the drain and source zones.
REFERENCES:
patent: 2994811 (1961-08-01), Senitzky
patent: 3321680 (1967-05-01), Arndt et al.
patent: 3593071 (1971-07-01), Janning
patent: 3836993 (1974-09-01), Jashi
patent: 4025940 (1977-05-01), Kimura et al.
LaRoche Eugene R.
Miyage National College of Technology
Shingleton Michael
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