MOS fabrication method with self-aligned gate

Details MOS fabrication method with self-aligned gate MOS fabrication method with self-aligned gate

1991-02-11

1992-08-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 53, 437229, H01L 21265

Patent

active

051399628

ABSTRACT:
MOS field-effect transistors connected in series on a semiconductor substrate are created by forming at least two first gate electrodes on the substrate, mutually separated by a certain distance, then depositing a polycrystalline conducting layer. The polycrystalline conducting layer is patterened, preferably using an etch-back process, to create a second gate electrode self-aligned between each pair of first gate electrodes. Source and drain diffusion layers are created in the substrate, using the first and second gate electrodes as a mask.

REFERENCES:
patent: 4738683 (1988-04-01), Blanchard et al.
patent: 4766089 (1988-08-01), Davids et al.
patent: 4994405 (1991-02-01), Jayakar
patent: 5017515 (1991-05-01), Gill

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