MOS Dynamic memory cells and method of fabricating the same

Details MOS Dynamic memory cells and method of fabricating the same MOS Dynamic memory cells and method of fabricating the same

1981-12-30

1985-01-08

Munson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 54, 357 59, 365149, H01L 2978, H01L 2702, H01L 2904, G11C 1124

Patent

active

044929730

ABSTRACT:
The MOS dynamic memory cell comprises a first electroconductive layer formed on a surface of a first region of a semiconductor substrate having a first conductivity type and an impurity concentration of less than 5.times.10.sup.14 cm.sup.-3 through a first insulating film, a second semiconductor region having a higher impurity concentration than the first semiconductor region and provided adjacent to one end of the first semiconductor region, a second electroconductive layer formed on the second semiconductor region through a second insulating film, and a third semiconductor region of a second conductivity type and provided adjacent to the second semiconductor region. The second electroconductive layer is used as a row line, whereas the third semiconductor region is used as a column line as well as a digit line. An inversion layer is formed on a surface of the first semiconductor region. The MOS dynamic memory cell is used to fabricate a MOS dynamic random access memory.

REFERENCES:
patent: 4004159 (1977-01-01), Rai et al.
patent: 4012757 (1977-03-01), Koo
patent: 4060738 (1977-11-01), Tasch et al.
patent: 4112575 (1978-09-01), Fu et al.
patent: 4115795 (1978-09-01), Masuoka et al.
patent: 4152779 (1979-05-01), Tasch et al.
patent: 4164751 (1979-08-01), Tasch
patent: 4225945 (1980-09-01), Kuo
patent: 4291322 (1981-09-01), Clemens et al.
Tasch et al., "The Hi-C RAM Cell Concept", IEEE Trans. Electron Devices, vol. ED-25, (1/78), pp. 33-41.

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