MOS device with a high voltage isolation structure

Details MOS device with a high voltage isolation structure MOS device with a high voltage isolation structure

2011-01-11

2011-01-11

Gurley, Lynne A. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257SE29019

Reexamination Certificate

active

07868422

ABSTRACT:
The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.

REFERENCES:
patent: 5618688 (1997-04-01), Reuss et al.
patent: 6207484 (2001-03-01), Kim et al.
patent: 2002/0190309 (2002-12-01), Takahashi et al.
patent: 2004/0224472 (2004-11-01), Hebert
patent: 95103764 (1995-02-01), None
patent: 584967 (2004-04-01), None
patent: 584967 (2004-04-01), None
patent: 98/28797 (1998-07-01), None

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