MOS decoder logic circuit having reduced power consumption

Details MOS decoder logic circuit having reduced power consumption MOS decoder logic circuit having reduced power consumption

1978-11-30

1981-06-23

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 365227, 365230, H03K 19094, H03K 1920, G11C 800

Patent

active

042753120

ABSTRACT:
The present invention relates to a transistor circuit, and more specifically to a static decoder circuit made up of a series circuit of a NOR logic gate circuit consisting of a plurality of MISFET's for receiving address signals through the gates, an inverter circuit for receiving the output of the logic gate circuit through the gate, a first MISFET for receiving the output of the logic gate circuit through the gate, and a second MISFET for receiving the output of the inverter circuit through the gate, wherein said NOR logic gate circuit and inverter circuit are connected to a ground terminal via a first switching MISFET which receives the control signals through the gate, and said series circuit is connected to a power supply terminal via a second switching MISFET which receives the control signals through the gate. According to the circuit of the present invention, said first and second switching MISFET's are rendered off by said control signals during the standby periods, such that the current pass is completely interrupted between the power supply terminal and the ground terminal in the decoder circuit, and the output of the decoder circuit is rendered to acquire the ground level.

REFERENCES:
patent: 3702926 (1972-11-01), Picciano et al.
patent: 3765003 (1973-10-01), Paivinen et al.
patent: 3778784 (1973-12-01), Karp et al.
patent: 3909806 (1975-09-01), Uchida
patent: 3936810 (1976-02-01), Dunn
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4027174 (1977-05-01), Ogata
patent: 4074237 (1978-02-01), Spampinato
patent: 4096584 (1978-06-01), Owen et al.

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