MOS Decoder circuit using phase clocking for reducing the power

Details MOS Decoder circuit using phase clocking for reducing the power MOS Decoder circuit using phase clocking for reducing the power

1980-11-26

1984-05-01

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 365230, H03K 19096, H03K 1920, G11C 800

Patent

active

044463863

ABSTRACT:
In a decoder circuit in which a transistor for reducing power use, which is supplied at its gate with a first control signal, is connected in series with a logical gate composed of a load transistor and a plurality of transistors which are respectively supplied at their gates with address signals, there is provided an off buffer circuit which comprises a first inverter for receiving the output of the logical gate and a second inverter for receiving the output of the first inverter. To a load transistor of the second inverter is provided a second control signal delayed in phase behind the first control signal and the output of the off buffer circuit is used as a decoded output of the address signal, so that the rise and fall of a word line is reduced.

REFERENCES:
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4063118 (1977-12-01), Nishimura
patent: 4185320 (1980-01-01), Takemae et al.
patent: 4198700 (1980-04-01), Aoyama et al.
patent: 4275312 (1981-06-01), Saitou et al.

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