MOS current sense circuit

Details MOS current sense circuit MOS current sense circuit

2001-10-16

2002-11-12

Vu, Bao Q. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S313000

Reexamination Certificate

active

06479975

ABSTRACT:

BACKGROUND OF THE INVENTION
1 Field of the Invention
The invention relates to a current sense circuit, and more particularly, to an MOS current sense circuit with improved accuracy.
2 Description of the Prior Art
Current sense circuits are widely used in integrated circuits. If a potentially large output, or load, current must be driven by an on-chip switch, a current sense circuit may be used to detect the relative or absolute value of this current. The current level may be monitored to prevent damage to the switch or to the integrated circuit from either a short circuit or a simple overloading.
Referring now to
FIG. 1
, a simplified schematic of a current sense circuit is illustrated. This circuit illustrates a problem common in current sense circuits of the art. In this circuit, a resistive load, R
LOAD
10
, is driven by a low-side, NMOS transistor M
OUT
14
. R
LOAD
10
is an external resistor that is coupled between an external voltage supply, V
EXT
22
, and the OUT pin of the circuit. M
OUT
14
is turned ON and OFF by the logic signal CONTROL
30
which is coupled to the gate of M
OUT
14
.
The current sense scheme of this circuit uses a simple current mirror approach wherein a mirroring device, M
SENSE
18
, creates a sense current, I
SENSE
, that is proportional to the load current, I
LOAD
. The NMOS transistor M
SENSE
18
may be constructed substantially smaller than M
OUT
14
. Since M
SENSE
18
receives the same gate drive as M
OUT
14
, both devices conduct at the same time. I
SENSE
is mirrored using the PMOS devices M
3
38
and M
4
42
to create the mirror current I
S2
.I
S2
flows through the sense resistor R
SENSE
46
to create a voltage at node B. The voltage at node B is then compared to a reference voltage, V
REF
50
, using a simple comparitor circuit
54
. If the voltage at B exceeds V
REF
50
, the comparitor enables the OC
58
, or over current, output.
A key problem in this approach is the operating characteristics of M
SENSE
18
and of M
OUT
14
. M
OUT
14
is operating in the linear, or ohmic, region. Therefore, variations in I
LOAD
cause variations in the drain-to-source voltage across M
OUT
14
. Further, since M
OUT
14
is designed to have a low ON resistance, this drain-to-source voltage drop is relatively small.
However, M
SENSE
18
is operating in a different region. Specifically, the presence of the mirroring device M
3
38
insures that a relatively large voltage exists at node A and, therefore, as the drain-to-source voltage of M
SENSE
18
. M
SENSE
18
may therefore be operating in a saturation region. The drain current of M
SENSE
18
may not correspond to the drain current of M
OUT
14
, even though both receive the same gate drive. Therefore, I
SENSE
may not proportionally correspond to I
LOAD
. On the contrary, if the circuit is altered such that M
SENSE
18
is operating in the linear region, then the drain-to-source voltage must somehow be carefully controlled to track that of M
OUT
14
in order to obtain a good current proportionality.
Several prior art inventions describe current sensing circuits. U.S. Pat. 5,877,617 to Ueda describes a load current sensing circuit. The gates and drains of the power and sensing MOSFETs are coupled together. A sensing resistor is coupled between the sensing transistor source and ground. Compensation resistors are used to improve temperature performance. U.S. Pat. No. 5,670,867 to Mitsuda teaches an MOS load current sensing circuit. A CMOS pair is used to feedback the drain-to-source voltage of the output device to a comparitor. A fixed voltage reference is used as the other comparitor input. U.S. Pat. No. 5,652,540 to Eilley discloses a load current sensing circuit for a bipolar driver.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable MOS current sense circuit.
A further object of the present invention is to provide a current sense circuit where the sense current is more accurately proportional to the load current.
A still further object of the present invention is to improve accuracy by operating both the load transistor and the sense transistor in the linear region and comparing the drain-to-source voltages.
Another still further object of the present invention is to provide an NMOS, low-side drive or a PMOS, high-side drive current sense.
Another still further object of the present invention is to provide an adjustable or trimmable current sense circuit to improve precision.
Another still further object of the present invention is to provide a current sense circuit that may be incorporated a into current limit.
In accordance with the objects of this invention, a new current sense circuit has been achieved. The current sense circuit comprises, first, a first MOS transistor having a gate, a drain, and a source. The gate is coupled to a control signal. The drain is coupled to a load such that a load current flows through the first MOS transistor when the control signal is ON. A second MOS transistor has a gate, a drain, and a source. The gate is coupled to the control signal. The drain is coupled to a constant current source such that the constant current flows through the second MOS transistor when the control signal is ON. The source is coupled to the source of the first MOS transistor. The first and second MOS transistors are operating in the linear region when the control signal is ON. Finally, a means to compare the first MOS transistor drain voltage and the second MOS transistor drain voltage is provided.


REFERENCES:
patent: 4553084 (1985-11-01), Wrathall
patent: 5563504 (1996-10-01), Gilbert et al.
patent: 5572161 (1996-11-01), Myers
patent: 5652540 (1997-07-01), Eilley
patent: 5670867 (1997-09-01), Mitsuda
patent: 5838192 (1998-11-01), Bowers et al.
patent: 5867014 (1999-02-01), Wrathall et al.
patent: 5877617 (1999-03-01), Ueda
patent: 5973550 (1999-10-01), Bowers et al.
patent: 6107789 (2000-08-01), Fryer et al.
patent: 6166530 (2000-12-01), D'Angelo

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