MOS capacitor with direct polycrystalline contact to grooved sub

Details MOS capacitor with direct polycrystalline contact to grooved sub MOS capacitor with direct polycrystalline contact to grooved sub

1988-03-21

1989-01-10

Clawson, Jr,, Joseph E.

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357 41, 357 54, 357 55, 357 59, 365149, H01L 2978

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047977191

ABSTRACT:
A MOS capacitor comprising a semiconductor substrate having a pair of spaced trenches in one surface. An isolation region is located in the substrate between the trenches and first polycrystalline silicon films are formed within each of the trenches directly on the substrate. Insulating films are formed on the first polycrystalline film, and a second polycrystalline film is formed on the insulating films. The first and second polycrystalline films function as first and second electrodes of the MOS capacitor and the insulating film as a dielectric layer of the capacitor.

REFERENCES:
M. Koyanagi et al., "Novel High Den., Stacked Cap. MOS RAM," Jap. J. A. P., vol. 18, 1979, Suppl. 18-1, pp. 35-42.
D. Kenney, "Reduced Bit Line Cap. in VMOS Devices," IBM Tech. Discl. Bull., vol. 23, #9, Feb. 1981, pp. 4052-4053.
Japanese Patent Abstracts., vol. 9, No. 159 (E-326) Jul. 4, 1985, JP 60038855(1).

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