MOS buffer immun to ESD damage

Details MOS buffer immun to ESD damage MOS buffer immun to ESD damage

1999-06-08

2001-09-11

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C361S091100, C361S119000

Reexamination Certificate

active

06288884

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuitry. More particularly, the present invention relates to a MOS buffer to ensure the triggering of an ESD protection circuit prior to the buffer during an ESD event.
2. Description of the Related Art
In sub-micron CMOS integrated circuits (ICs), electrostatic discharge, ESD hereinafter, is a reliability concern. For example, U.S. Pat. No. 5,465,189 discloses a low voltage triggering semiconductor controlled rectifier, LVTSCR hereinafter, to protect the integrated circuit from ESD damage. The equivalent circuit diagram of the conventional LVTSCR is schematically illustrated in FIG.
1
.
As shown in
FIG. 1
, an IC core circuit
1
is coupled to a bonding pad
2
through an output buffer
10
. An LVTSCR
11
is provided on the path between the pad
2
and the output buffer
10
. The LVTSCR
11
can be triggered to conduct an ESD discharge current at a low voltage of about 10~15 Volts so as to bypass the ESD stress occurring to the pad
2
. Accordingly, the output buffer
10
or even the core circuit
1
can be protected against ESD damage. Typically, the output buffer
10
includes a PMOS transistor
12
and an NMOS transistor
13
connected in series between VDD and VSS power rails. Referring to
FIG. 2
, the LVTSCR
11
fabricated onto a P-type semiconductor substrate
20
is illustrated in a cross-sectional view.
In
FIG. 2
, an N-well
21
is formed on the semiconductor substrate
20
in which a P-type doped region
22
is provided. An N-type doped region
23
is formed in the P-type substrate
20
. Further, another N-type doped region
24
with one portion formed in the P-type substrate
20
and another portion formed in the N-well
21
is provided between the P-type doped region
22
and the N-type doped region
23
. An N-type contact region
25
and a P-type contact region
26
are formed in the N-well
21
and the P-type semiconductor substrate
20
as ohmic contacts thereof, respectively. A gate structure, including a dielectric layer
27
and an electrode layer
28
from bottom to top, is provided to overlie a portion of P-type semiconductor substrate
20
between the N-type doped regions
23
and
24
.
As shown in
FIG. 2
, the P-type doped region
22
, N-well
21
, and P-type semiconductor substrate
20
constitute, respectively, the emitter, base, and collector of a PNP bipolar junction transistor
14
. Alternatively, the N-well
21
, P-type semiconductor substrate
20
, and N-type doped region
23
constitute, respectively, the collector, base, and emitter of an NPN bipolar junction transistor
15
. The PNP transistor
14
and NPN transistor
15
connected in such a manner are termed a lateral semiconductor controlled rectifier. The N-type doped regions
23
-
24
and gate structure
27
-
28
constitute a MOS-like device
18
. However, resistors
16
and
17
indicate the spreading resistances R of the N-well
21
and the spreading resistance R
2
of the P-type semiconductor substrate
20
, respectively.
Referring further to
FIG. 2
, the N-type contact region
25
and the P-type doped region
22
are connected to the pad
2
, where the N-type doped region
23
, P-type contact region
26
, and electrode layer
28
are all connected to the VSS power rail. During an ESD event, the MOS-like device
18
enters avalanche breakdown to trigger the lateral semiconductor controlled rectifier for conducting a discharge current and thus bypasses the ESD stress occurring to the pad
2
. Thus, the core circuit
1
can be protected from ESD damage. Accordingly, the LVTSCR
11
has a trigger voltage as low as the breakdown voltage of the MOS-like device
18
.
To ensure that the PMOS transistor
12
and NMOS transistor
13
are immune to ESD damage, the MOS-like device
18
is typically provided with a gate length greater than that of the PMOS transistor
12
or NMOS transistor
13
. However, the larger layout area thus required is unfavorable given the trend of high integration. Moreover, another conventional buffer formed by connecting resistors
31
or
32
between the pad
2
and respective drain of the PMOS transistor
12
and the NMOS transistor
13
, is proposed to increase the effective resistance along the path from the pad
2
to the VDD rail, or from pad
2
to the VSS rail. Although effectively impeding ESD stress from being bypassed through the PMOS transistor
12
or NMOS transistor
13
, the resistors
31
and
32
may diminish the performance of the output buffer during circuit operation.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a MOS buffer which ensures a semiconductor controlled rectifier is triggered during an ESD event to bypass the ESD stress occurring to an IC pad before the MOS buffer.
To achieve the above-identified object, the present invention provides a buffer integrated with an ESD protection circuit onto a semiconductor substrate. The ESD protection circuit is triggered by means of a MOS-like device having a first spreading resistance during an ESD event. The buffer comprises a plurality of finger-type devices connected in parallel, where each finger-type device is provided with a second spreading resistance less than the first spreading resistance.
Therefore, the buffer of the present invention is provided with at least one MOS transistor configured with multi-finger layout to form a plurality of finger-type devices connected in parallel. Each finger-type devices provides a bipolar junction transistor with the second spreading resistance less than that of the bipolar junction transistor provided by the MOS-like device in the ESD protection circuit so as to impede the conduction of the MOS transistor in the buffer during an ESD event. Moreover, even though the MOS transistor of the buffer and the MOS-like device of the ESD protection circuit may simultaneously enter breakdown, the bipolar junction transistors are parasitic onto the finger-type devices, and thus cause the base resistances to increase the holding current when entering snapback and uniformly bypass the ESD discharge current. In addition, the spacing between the contact and gate can be further decreased to reduce the required layout area.


REFERENCES:
patent: 5623156 (1997-04-01), Watt
patent: 5751042 (1998-05-01), Yu
patent: 5895940 (1999-04-01), Kim

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