MOS buffer circuit

Details MOS buffer circuit MOS buffer circuit

1977-03-18

1978-07-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307214, 307215, 307237, 307270, 307DIG1, H03K 1908, H03K 1934, H03K 1936, H03K 1940

Patent

active

041017889

ABSTRACT:
A MOS control circuit for controlling an output signal, said control circuit being coupled to first and second sources of potential. The magnitude or peak-to-peak amplitude of the first source of potential is greater than the magnitude developed by the second source of potential. The control circuit output signal has a waveshape magnitude of desired dimension somewhere between the magnitude of the second source of potential and the magnitude of the first source of potential. In order to accomplish this, a first inverter receives and inverts an input signal and produces an output potential at a node. A clamping circuit reduces the potential at the node by a desired amount. A source follower is driven by the potential at the node and also receives the input signal. The output of the source follower is the control output signal.

REFERENCES:
patent: RE27305 (1972-03-01), Polkinghorn et al.
patent: 3675043 (1972-07-01), Bell
patent: 3775693 (1973-11-01), Proebsting
patent: 3986044 (1976-10-01), Madland et al.
Homan, "FET Depletion Load Push-Pull Logical Circuit"; IBM Tech. Discl. Bull., vol. 18, No. 3, pp. 910-911; Aug. 1975.
Hayashi et al., "Design of ED-MOS Buffer"; Electronics and Communications in Japan (pub.), vol. 55-c, No. 10; pp. 107-114; Oct. 1972.

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