MOS antifuse with low post-program resistance

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S529000

Reexamination Certificate

active

07064410

ABSTRACT:
A semiconductor device having an increased intersection perimeter between edge regions of a first conductor and portions of a second conductor is disclosed. In one embodiment, the intersection perimeter is the region where the perimeter of a gate structure overlaps an active area. The intersection perimeter between the conductors directs the breakdown of the dielectric material, increasing the likelihood that the programming event will be successful. In at least one embodiment, the portion of a current path that travels through a highly doped area is increased while the portion that travels through a non-highly doped area is decreased. This decreases post-program resistance, leading to better response time for the device.

REFERENCES:
patent: 4914055 (1990-04-01), Gordon et al.
patent: 5219782 (1993-06-01), Liu et al.
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5395797 (1995-03-01), Chen et al.
patent: 5469077 (1995-11-01), Cox
patent: 5493147 (1996-02-01), Holzworth et al.
patent: 5502000 (1996-03-01), Look et al.
patent: 5587613 (1996-12-01), Iranmanesh
patent: 5625220 (1997-04-01), Liu et al.
patent: 5793094 (1998-08-01), Sanchez et al.
patent: 5856213 (1999-01-01), Love et al.
patent: 5913138 (1999-06-01), Yamaoka et al.
patent: 5970372 (1999-10-01), Hart et al.
patent: 6020777 (2000-02-01), Bracchitta et al.
patent: 6069064 (2000-05-01), Cutter et al.
patent: 6087707 (2000-07-01), Lee et al.
patent: 6096580 (2000-08-01), Iyer et al.
patent: 6146925 (2000-11-01), Dennison
patent: 6221729 (2001-04-01), Dennison
patent: 6388305 (2002-05-01), Bertin et al.
patent: 6574763 (2003-06-01), Bertin et al.
patent: 9055475 (1997-02-01), None
“Impact of Shallow Trench Isolation on Reliability of Buried and Surface Channel Sub-um PFET”, Tonti, et al., 1995, pp. 24-29.
International Application No. PCT/US94/11002, Look, et al.
International Application No. PCT/US94/01619, Hall, et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

MOS antifuse with low post-program resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS antifuse with low post-program resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS antifuse with low post-program resistance will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3665228

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.