More robust alignment mark design

Details More robust alignment mark design More robust alignment mark design

1999-02-22

2002-02-05

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

Reexamination Certificate

active

06344698

ABSTRACT:

DESCRIPTION
1. Field of the Invention
The present invention relates to robust alignment marks and, in particular, to alignment marks which improve the accuracy of an alignment during the manufacturing of a semiconductor device. The improved accuracy is achieved in the present invention by providing alignment mark designs which enhance the symmetrical signals emitting from asymmetric microstructures. Moreover, the alignment marks of the present invention are highly resistant to damages caused by semiconductor processing steps used in manufacturing semiconductor devices thus improving the reliability and accuracy of the alignment process.
2. Background of the Invention
In very large scale integration (VLSI) photolithographic processes, a mask comprising a desired circuit pattern must be precisely aligned with a semiconductor wafer, or with a pattern previously formed on the wafer, in order to ensure proper placement of the projected image. Moreover, in order to increase integration density, VLSI chips typically employ multiple layers formed by successive image projection steps. In the photofabrication of such multilayer semiconductor devices, the precise registry of the successive images is extremely critical.
Measurement overlays are generally employed in the prior art to confirm that successively projected circuit patterns have been positioned accurately with respect to each other. To obtain the necessary mask to wafer alignment, marks are placed in the peripheral regions of the mask and the wafer respectively. These marks are detected by a photo-optical detector of the exposure tool. A precision alignment system is then used to measure relative positions of the wafer and mark such that the current level is exposed in the correct position relative to the prior level.
Numerous alignment marks are known in the prior art which have a variety of shapes, patterns and configurations. The exact design of a prior art alignment mark is oftentimes dependent on the photo-optical detection system being used. Examples of some prior art alignment marks are found, for instance, in U.S. Pat. No. 5,601,957 to Mizutani, et al.; U.S. Pat. No. 5,702,567 to Mitsui, et al.; 5,760,484 to Lee, et al.; 5,777,392 to Fujii; and 5,808,742 to Everett, et al.
Typically, prior art alignment marks, such as those described in the above patents, comprise a set of long, narrow trenches or lines which are placed a significant distance apart (10 microns or greater). One such prior art alignment mark is shown in FIGS.
1
(
a
)-(
b
). Specifically, FIG.
1
(
a
) comprises a prior art fine alignment mark. This prior art fine alignment mark of a set of parallel trenches, i.e. lines, which are spaced apart by a great distance. The parallel lines are placed on the wafer or mask on a 45° angle. FIG.
1
(
b
), on the other hand, shows a prior art intermediate alignment mark consisting of two sets of parallel trenches that crisscross each other to form a “X” shaped design. As is known to those skilled in the art, the intermediate alignment marks are employed to provide a course alignment of the image or pattern, whereas the fine alignment mark is used for greater alignment precision.
Another type of alignment mark design currently being employed in semiconductor manufacturing is shown in FIG.
2
. Specifically, the alignment mark of
FIG. 2
comprises a set of long, narrow trenches or lines that are arranged in a 90° orientation.
One major problem with prior art alignment marks of the kind illustrated above is that some of the processing steps employed in fabricating the semiconductor device, such as chemical mechanical polishing (CMP) or grinding, damage the alignment marks so that the alignment/exposure tool either can't detect the mark or it detects a distorted image so the measured position is incorrect. This results in misalignment of the various layers of the structure causing the need to repeat the various processing steps. This misalignment increases cost as well as processing times.
Another problem with prior art alignment marks is that, if the alignment mark is damaged during processing, the signal generated from these asymmetric microstructures may not be totally symmetrical. Thus, alignment marks of the prior art oftentimes provide an asymmetrical signal which reduces the detection capability of the prior art alignment marks.
There is thus a need for developing new alignment marks which are more robust than existing alignment marks currently being employed. Specifically, new alignment marks are needed which are substantially resistant to damages caused during the production of a semiconductor device. Such alignment marks will be beneficial in the semiconductor industry since they will lower the production cost and time required for fabrication of an individual semiconductor device, e.g. integrated circuit, transistor, etc. Moreover, new alignment marks are needed which substantially eliminate the asymmetric signal which can be generated by such microstructures.
SUMMARY OF THE INVENTION
The present invention provides new alignment mark designs that are robust. The term “robust” is used herein to denote an alignment mark which is substantially resistant to damages caused during device manufacturing. The robust nature of the alignment marks of the present application allows for easier detect and better alignment of the circuit pattern on the wafer. It is noted that the term “alignment mark” as used herein refers to intermediate or global alignment marks as well as fine alignment marks.
In accordance with one embodiment of the present invention, the alignment mark comprises a set of geometrical defined shapes, i.e. images, that are staggered in a checkerboard configuration to achieve more left and right line edges in a small space. The size of the geometrical images used in the checkerboard arrangement is chosen to be within the resolving capability of the exposure tool, so that the shapes can be printed. The shape size is however smaller than the resolving capability of the alignment system resulting in the alignment system's detector seeing only one overall image from the series of edges. The small staggered checkerboard images provide a strong, robust signal which is more resistant to variability in prior processing steps than the prior art alignment marks which utilize a set of long, narrow trenches placed a significant distance apart.
The term “checkerboard” is used herein to denote a configuration (elongated, square, rectangular, circular, etc.) wherein geometrical defined shapes such as squares, triangles, circles, diamonds and other like shapes, are arranged in a pattern such that the shapes are staggered and spaced apart from each other. This arrangement provides a blend of left and right edges which generates more symmetrically aligned signals than heretofore possible with prior art alignment marks.
Another embodiment of the present invention is to modify the outermost edges of the checkerboard-containing alignment mark described hereinabove so that the same are not visible to the alignment detector. This results in alignment system seeing the same number of left vs. right edges in a single scan which will reduce the effects of differential edge damage by prior level processing steps. The edge structure of the alignment marks of the present invention can be changed in various ways. On variation employed in the present invention is to change from an edge of a bar to two edges of a triangle.
In any of the above embodiments, the prior art problem identified in the background section of the application has been overcome by providing a series of closely spaced smaller images, rather than one large image. The smaller images are less susceptible to polish damage, and the proximity of other small images makes them even more resistant to polish damage. In addition, alignment will be more robust because each mark of the present application provides multiple edges for the detectors and the size is chosen to provide the same signal from the detector that the system handles.
The present invention also prov

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