Monostable logic gate in a programmable logic array

Details Monostable logic gate in a programmable logic array Monostable logic gate in a programmable logic array

1986-07-29

1988-10-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307469, 307481, 307582, 307585, 307594, 307605, H03K 3355

Patent

active

047790105

ABSTRACT:
An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead to ground in response to the signal (IN1) on the first input lead and a second NMOS transistor (60) which couples the output lead to ground in response to the signal (IN2) on the second input lead. A buffer (76) having a high output impedance is coupled to the output lead and tends to maintain the output lead in a constant state. When the signal on the first input lead goes high, the first NMOS transistor turns off and a PMOS transistor (64) turns on, thereby coupling the output lead to a high voltage source for a predetermined time period. If the second NMOS transistor is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer maintains the output lead in the high state.

REFERENCES:
patent: 3862440 (1975-01-01), Suzuki et al.
patent: 4437024 (1984-03-01), Wacyk
patent: 4518873 (1985-05-01), Suzuki et al.
patent: 4570083 (1986-02-01), Nakaizumi
Hines, "Combined Single-Shot and Delay Circuit", IBM T.D.B., vol. 18, No. 2, Jul. 1967, pp. 184-185.
Chang, "Integrated FET Single-Shot", IBM T.D.B., vol. 16, No. 1, Jun. 1973, pp. 315-316.
Kazmi, "Design Prototypes Quickly with Programmable Arrays", 2328 Electronic Design, vol. 29, Feb. 19, 1981, No. 4, pp. 121-124.

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