Monophase logic

Details Monophase logic Monophase logic

1990-06-18

1991-10-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307542, 307451, 307550, 307548, 307448, 307449, H03K 19003, H03K 19017, H03K 1704, H03K 17687

Patent

active

050618644

ABSTRACT:
Intermediate path splitting circuit arrangements are coupled between the input node and output stage of an IC defining a plurality of different signal propagation paths. A relatively higher speed output pullup turn on signal progagation path is coupled between the input node and the output pullup transistor element for turning on the output pullup transistor element at relatively higher speed in response to a first input data signal. A relatively slower speed output pulldown turn off signal propagation path turns off the output pulldown transistor element at a relatively slower speed in response to the first data input signal. Similar circuit arrangements are provided for relatively high speed turn on of the pulldown transistor element and relatively low speed turn off of the pullup transistor element. Control of turn on and turn off of the respective output pullup and pulldown transistor elements is from separate output driver nodes for higher speed operation. The separate split paths are provided by sequences of internal stages with skewed conductance pullup and pulldown elements. A cutoff circuit cuts off the output pullup and pulldown transistor elements a time delay after transmission of an output data signal to reduce simultaneous conduction. A data saver circuit coupled to the final output node saves the output data signal during cutoff. The high speed on logic signal propagation circuits are applicable in CMOS circuits and other logic families.

REFERENCES:
patent: 4885485 (1989-12-01), Leake et al.
patent: 4959561 (1990-09-01), McDermott et al.
patent: 4959565 (1990-09-01), Knecht et al.
patent: 4977341 (1990-12-01), Stein
patent: 4985643 (1991-01-01), Proebsting
patent: 4992676 (1991-02-01), Gerosa et al.
Zhang, "An Improvement For Domino CMOS Logic", 1987 CEE, pp. 53-59.
Oklobdzija et al., ". . . CMOS Domino Logic", 1985 IEEE CICC, pp. 334-337.
Pretorius et al., "Latched Domino CMOS Logic", 1986 IEEE JSSC, pp. 514-522.
Krambeck et al., "High Speed Compact Circuits with CMOS", 1982 IEEE JSSC, pp. 614-619.

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