Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2003-06-12
2004-09-14
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
Reexamination Certificate
active
06790744
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention generally relates to silicon semiconductor chips and more particularly to an improved semiconductor chip that includes thermoelectric energy converters.
Heat generation and heat transport in deep sub-micron very large scale integration (VLSI) and radio frequency (RF) circuits is of increasing concern under normal device operation. In RF circuits, significant heat generation by the power amplifiers in the transmitter circuitry can adversely affect circuit performance (noise, speed, and reliability). In addition, a significant heat source will induce a significant thermal gradient across the chip. Use of the most advanced technologies such as (silicon-on-insulator) SOI and low-dielectric constant (low-K) inter-level dielectric (ILD) materials further aggravates the thermal management problem for deep sub-micron VLSI and RF circuits. For silicon-on-insulator (SOI) technology, the thermal conductivity of the insulator layer is more than two orders of magnitude lower than the usual Si substrate (0.66 W/m-K vs. 148 W/m-K). Heat generated above the oxide layer is less able to dissipate into the substrate, resulting in self heating. Thus high currents flowing in the channel lead to an increase in the channel temperature, which can degrade device performance and reliability. Use of low-K dielectrics for advanced interconnect passivation has a similar effect. Low-k dielectric materials have relatively lower thermal conductivities than conventional glass materials such as Silane oxide (0.19 vs 1.07 W/m-K, respectively). Heat dissipation from metal interconnects carrying high current is therefore much less effective when a low-K material is used for metal passivation. The resultant increase in wire temperature can induce electromgration and stress voiding problems.
Ordinarily, a device on a silicon chip is only one of several which generate heat. Such heat, together with that from all other devices on the chip, acts to raise the average temperature of the substrate. If only a single device, or a small fraction of those on the chip, operates at a temperate higher than the ambient average, it can be cooled by removing heat locally and depositing it into the ambient reservoir far from the device being cooled. This will raise the ambient temperature of the reservoir somewhat, but because of the size of the reservoir, the magnitude will be relatively small. However, if all devices are cooled, the average temperature of the reservoir will rise to the point where the reservoir will supply heat to the device being cooled as fast as the cooling devices can remove it. Therefore, there is a need to provide thermal isolation of the device being cooled from the substrate, such that the temperature of the cooled device is below that of the average substrate temperature.
In order to intelligently manage on-chip thermal generation, there is a need for monolithically integrated solid-state energy converters that provide localized cooling capabilities and on-chip power generation for future high-speed, low-power, and high performance circuits. The invention described below provides such a structure and method for making such a structure.
BRIEF SUMMARY OF THE INVENTION
In view of the foregoing problems, disadvantages, and drawbacks, the present invention has been devised, and it is an object of the present invention to provide a structure and method for improved semiconductor chip devices that include thermoelectric energy converters, and thermoelectric coolers in particular.
In order to accomplish the object(s) suggested above, there is provided, according to one aspect of the invention, a semiconductor structure that includes a substrate having at least one integrated circuit heat generating structure. The invention has at least one integrated circuit cooling device on the substrate surrounding the heat generating structure. The cooling device is adapted to remove heat from the area around the heat generating structure. The cooling device includes a cold region and a hot region. The cold region is positioned adjacent the heat generating structure.
The invention also presents a method of creating an integrated thermoelectric cooling device. The method forms a strained silicon layer over a substrate, patterns the strained silicon layer to form a mesa island, forms a superlattice structure on the substrate adjacent the mesa island, alternately dopes N-type and P-type regions within the superlattice structure, removes undoped regions of the superlattice structure, and forms a patterned metal conductor to connect N-type and P-type doped regions of the super lattice structure. The invention forms a strained silicon layer by epitaxially growing the strained silicon layer. The doping process can comprise a series of masking and doping processes that individually create the N-type and P-type regions within the superlattice structure.
REFERENCES:
patent: 3635037 (1972-01-01), Hubert
patent: 4054478 (1977-10-01), Linnon
patent: 4935864 (1990-06-01), Schmidt et al.
patent: 5522216 (1996-06-01), Park et al.
patent: 5550387 (1996-08-01), Elsner et al.
patent: 5608568 (1997-03-01), Blodgett et al.
patent: 5747728 (1998-05-01), Fleurial et al.
patent: 5900071 (1999-05-01), Harman
patent: 5956569 (1999-09-01), Shiu et al.
patent: 6060656 (2000-05-01), Dresselhaus et al.
patent: 6100463 (2000-08-01), Ladd et al.
patent: 6105381 (2000-08-01), Ghoshal
patent: 6222113 (2001-04-01), Ghoshal
patent: 6230497 (2001-05-01), Morris et al.
patent: 6384312 (2002-05-01), Ghoshal et al.
patent: 6403874 (2002-06-01), Shakouri et al.
patent: 2002/0033188 (2002-03-01), Shakouri et al.
patent: 2002/0063327 (2002-05-01), Chu et al.
patent: 2002/0092557 (2002-07-01), Ghoshal
patent: 2002/0113289 (2002-08-01), Cordes et al.
Chen Fen
Sullivan Timothy D.
Chadurjian, Esq. Mark F.
Coleman W. David
McGinn & Gibb PLLC
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