Monolithically integrated semiconductor circuit including I.sup.

Details Monolithically integrated semiconductor circuit including I.sup. Monolithically integrated semiconductor circuit including I.sup.

1983-09-02

1984-09-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 92, H03K 19091

Patent

active

044699638

ABSTRACT:
Monolithically integrated semiconductor circuit having I.sup.2 L cells each including a transistor and an injector, further circuit parts, a supply voltage being a multiple of a supply voltage required for operation of individual I.sup.2 L cells in which a corresponding number of I.sup.2 L cells are connected in series in chain fashion with respect to a first and a second supply terminal of the circuit furnishing the supply voltage for the circuit and each being acted upon by an operating potential, the injector of an I.sup.2 L cell forming a first chain link being tied to the first supply terminal of the circuit; the emitter of the transistor of the I.sup.2 L cell forming the first chain link being tied to the injector of a further I.sup.2 L cell forming a second chain link; the injector of an I.sup.2 L cell forming a third chain link being tied to the emitter of the transistor of the I.sup.2 L cell forming the second chain link, further I.sup.2 L cells similarly connected to the respective preceding chain link forming a respective chain link completing the chain, the emitter of this I.sup.2 L cell being connected to the second supply terminal of the circuit carrying the reference potential of the circuit, and the injector of this last I.sup.2 L cell being connected to the emitter of the transistor of the I.sup.2 L cell forming the next to the last chain link, including a further I.sup.2 L cell assigned to at least one of the links of the chain formed by I.sup.2 L cells connected in series with respect to their supply potentials.

REFERENCES:
patent: 4013901 (1977-03-01), Williams
patent: 4071774 (1978-01-01), Tokumara et al.
patent: 4091296 (1978-05-01), Suzuki et al.
patent: 4109162 (1978-08-01), Heuser et al.
patent: 4137465 (1979-01-01), Hart
patent: 4243896 (1981-01-01), Chapron
patent: 4256984 (1981-03-01), Kojima
patent: 4270059 (1981-05-01), Nishizawa et al.
K. Kaneko, T. Okabe and M. Nagata from "IEEE Journal of Solid State Circuits" (Apr. 1977), SC12, pp. 210 to 212, Entitled Stacked I.sup.2 L Circuit.

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