Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
2000-10-30
2001-09-11
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S544000
Reexamination Certificate
active
06288594
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to high-voltage and low-voltage selection circuits for non-volatile memories, and in particular, is directed to a selector integrated monolithically to a CMOS technology high switching-speed circuit for memories.
BACKGROUND ART
Integrated circuits more and more frequently involve the provision of different voltages for distribution to the circuit interior according to an activated operative phase. For instance, different voltages are required in semiconductor non-volatile memory (FLASH, EPROM, E
2
PROM) devices for the purpose of biasing wordlines during the different functional phases of the device. For a NOR memory architecture, for example, read operations involve biasing the wordline of an addressed cell to the same voltage as the supply voltage (V
dd
=3 or 5 Volts), whereas suitably higher voltages (e.g., Vpp=12 Volts) must be applied during the programming phase. Vdd is the supply voltage from an external source of the device, and Vpp may either be an externally supplied voltage, or a voltage generated internally from Vdd. With multi-level memory devices, moreover, a wordline bias voltage during a reading phase would exceed the value of the supply voltage Vdd (normally of 3 or 5 Volts). In order to allocate a larger number of levels than two in a reliable manner, the range of viable cell currents must be expanded to at least 100-120 &mgr;A; such current values are only possible, however, where gate voltages in the 5 to 6 Volts range are adopted. In addition, during specific functional phases (such as those activated for testing purposes), the wordline of a selected cell must be brought to an analog voltage in the 0 to VPP range for reading in the DMA (Direct Memory Access) mode, as the skilled ones in the art will recognize.
Integrated circuits thus operated are of necessity to incorporate a selector, which will be controlled by appropriate control signals to take up and distribute a desired voltage each time to the involved blocks.
Specifically in the instance of a non-volatile memory, there are basically two voltage lines (hereinafter referenced LV and HV) to be taken into account for the biasing of the wordlines, and the selector is mainly utilized to bias the wordlines. In this case, the selector will switch the power supply to the decoding final stages, as shown in
FIG. 1
of the drawings, between the low LV and high HV voltages according to whether an addressed cell is to be read or programmed.
Examples of prior selectors are disclosed in European Patent Application No. 98830332.7 by this Applicant.
The most commonly utilized programming technique (referred to as the program-verify algorithm) consists of applying, to the control gate of a selected cell, a high-voltage HV pulse (corresponding to the injection of hot electrons into the floating gate, and therefore, to the cell programming phase), followed by a low-voltage LV pulse during which the programmed state of the cell is “verified” by a read (verify) operation. If the programmed state of the cell matches the desired state, the procedure is stopped; otherwise, the program process is -continued with the application of a new high-voltage HV pulse.
In a multi-megabit memory, the selector output node OUT has a high capacitive load (for example, a load of about 800 pF for 4096 wordlines). In such context, of special concern are the HV/LV and LV/HV switching times and the settling times of the voltages on the selected line, especially with internal programming, that is a programming implemented through circuit blocks integrated to the device inside. In fact, one of the advantages of internal rather than external programming (i.e., as implemented by a special programming apparatus) is its speed, understood as the durations of the program and verify pulses being short, and short being, accordingly, the overall programming procedure In particular, as an illustration of magnitude, a typical duration can range from a hundred &mgr;s per pulse, for external programming, to one &mgr;s per pulse for internal programming. It can be readily appreciated that, when operating in such a range, the switching and settling times become critical parameters.
This problem acquires special importance where the generator(s) of the voltage to be distributed following a switch in the control signal has(have) a high output impedance. In that case, unless appropriate measures are taken, the switching/settling time can become too long, in view of the high capacitive load present on the node “OUT”. This is the case, for example, of a voltage LV generated by an integrated voltage generator (or generators), i.e. of the charge pump type, whose output impedance is indeed high. Thus, the HV/LV switchings have, in this case, the above referred drawbacks.
On the other hand, during complementary LV→HV switchings no such problems are supposed to exist, since the HV voltage is assumedly supplied from a low output impedance generator.
The underlying technical problem of this invention is to provide a monolithically integrated selector for electrically programmable memory cell devices, whereby the operations can be carried out at a faster rate.
DISCLOSURE OF INVENTION
This problem is solved by a monolithically integrable voltage selector as previously indicated and defined in claim
1
.
The features and advantages of a voltage selector according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5021680 (1991-06-01), Zaw Win et al.
patent: 5187396 (1993-02-01), Armstrong, II et al.
patent: 5517153 (1996-05-01), Yin et al.
patent: 5534801 (1996-07-01), Wu et al.
patent: 5570061 (1996-10-01), Shimoda
Manstretta Alessandro
Pierin Andrea
Torelli Guido
Fleit Kain Gibbons Gutman & Bongini P.L.
Galanthay Theodore E.
Gibbons Jon A.
STMicroelectronics S.r.l.
Tran Toan
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