Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Patent
1998-01-09
1999-09-14
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
257552, 257572, H01L 2970, H01L 29735
Patent
active
059527056
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a semiconductor arrangement.
BACKGROUND INFORMATION
A semiconductor arrangement is described in European Patent No. 99 897, where into a substrate that is weakly doped with a first conductivity type is introduced a region of a second conductivity type, which, together with the substrate, forms a p-n junction. To influence the breakdown voltage between the introduced region and the substrate, a cover electrode, which is separated from the substrate by a thin oxide layer, is applied to the surface. The breakdown voltage of the p-n junction is regulated by adjusting the potential of this cover electrode by means of a voltage divider.
Likewise disclosed by European Patent No. 179 099 is a semiconductor arrangement of this kind, where the voltage divider is formed by variably doped integrated resistors. This achieves a certain compensation of the temperature dependency of the breakdown voltage. In this context, additional process steps are required because of the variably doped divider resistors. Furthermore, resistors of this kind require a comparatively large chip surface.
SUMMARY OF THE INVENTION
The advantage of the semiconductor arrangement of the present invention is that the temperature dependency of the breakdown voltage is compensated for quite efficiently. In this context, no additional process steps are needed to produce the voltage divider, and the need for chip surface for the integrated voltage divider is minimal.
The elements having positive temperature coefficients are formed quite simply with resistors, Zener diodes, or combinations thereof. For the component having a negative temperature coefficient, a transistor is simply used. The transistor has an emitter-base voltage which exhibits a negative response to temperature changes. The transistor is expediently integrated quite compactly into the substrate, where the introduced region also serves as a collector for the transistor. To achieve a very precisely defined breakdown voltage, it is advantageous to use a heavily doped region with the conductivity type of the substrate in the region of the space charge region.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a cross-section through a conventional semiconductor arrangement.
FIG. 2 illustrates a cross-section through a semiconductor arrangement, according to an embodiment of the present invention, with the voltage divider symbolically represented.
FIG. 3 illustrates the cross-section of FIG. 2 with the diffusion regions introduced for the transistor, according to an embodiment of the present invention.
FIG. 4 illustrates a plan view of an exemplary embodiment according to the present invention.
FIG. 5 illustrates a plan view of an exemplary embodiment according to the present invention.
FIG. 6 illustrates a plan view of an exemplary embodiment according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 illustrates a semiconductor arrangement in accordance with European Patent No. 99 897. The semiconductor arrangement has a substrate with an upper weakly n-doped layer 1 and a bottom heavily n-doped layer 2. The bottom layer is contacted by a metal layer 2a on the reverse side. Introduced into the top side of the substrate, into n-layer 1 are a weak p-diffusion 3 and a strong n-diffusion 4, referred to in the following as .pi.-diffusion 3 and N+ diffusion 4. Provision is made on the top side of the substrate for a covering oxide layer 5 with a covering electrode 6 mounted thereon. Covering electrode 6 and covering oxide 5 cover the region of n-layer 1 disposed between .pi.-diffusion 3 and N+ diffusion 4. Provision is also made for a connection metallization 3a for contacting .pi.-region 3. To assure an ohmic contact, also disposed beneath region 3a is a heavy p-doping, which is not shown here, however, for the sake of clarity. Metallization 3a is connected to the negative pole, and metallization 2a to the positive pole of an operating voltage U. Covering electrode 6 is connected to the tap of a voltag
REFERENCES:
patent: 4284334 (1981-08-01), Magel
patent: 4677369 (1987-06-01), Bower
patent: 4742021 (1988-05-01), Burnham et al.
patent: 4766469 (1988-08-01), Hill
patent: 5077590 (1991-12-01), Fujihira
patent: 5449949 (1995-09-01), Michel et al.
patent: 5466959 (1995-11-01), Goerlach et al.
patent: 5479046 (1995-12-01), Flohrs et al.
patent: 5502338 (1996-03-01), Suda et al.
patent: 5521421 (1996-05-01), Furuhata
patent: 5545914 (1996-08-01), Kumano
Goerlach Alfred
Michel Hartmut
Pluntke Christian
Chaudhuri Olik
Coleman William David
Robert & Bosch GmbH
LandOfFree
Monolithically integrated planar semi-conductor arrangement with does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Monolithically integrated planar semi-conductor arrangement with, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Monolithically integrated planar semi-conductor arrangement with will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1512490