Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2002-03-22
2003-12-30
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S011000, C257S012000, C257S015000, C257S024000, C257S037000, C257S138000, C257S190000
Reexamination Certificate
active
06670652
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a monolithically integrated Enhancement/Depletion (E/D) mode High-Electron Mobility Transistor (HEMT) and a pseudomorphic High-Electron Mobility Transistor (hereinafter referred to as ‘(p-)HEMT’) and method for fabricating the same, and more particularly, to an E/D mode (p-)HEMT having a uniform threshold voltage on a monolithic substrate and method for fabricating the same.
BACKGROUND ART
In general, the HEMT or p-HEMT as a compound semiconductor device has excellent speed characteristics compared with those of electronic devices based upon silicon due to its excellent electron transport properties, and thus is widely used in microwave or millimeter-wave device applications operating in the frequency range between 10 GHz and 100 GHz. The (p-)HEMT device technology is very important because it has advantages such as the highest operational frequency among field effect transistors and the extremely low high-frequency noise. The (p-)HEMT device technology is applied for developing circuits or components for broadband wireless communication systems operating at millimeter-wave frequency or for high-speed optical communication systems operating at several tens of Gbps or more.
In general, the (p-)HEMT is divided into a depletion mode transistor having a negative value of threshold voltage V
Th
and an enhancement mode transistor having a positive value of threshold voltage V
Th
. The depletion mode transistor is generally used in fabrication of a Monolithic Microwave Integrated Circuit (MMIC).
FIG. 1A
is a circuit diagram of an integrated circuit using depletion mode (p-)HEMTs
10
and
11
only. Referring to
FIG. 1A
, two power supplies such as VDD having a positive voltage and −V
G
having a negative voltage are required in order to operate this circuit. Therefore, when a module for wireless communication terminals is fabricated using an integrated circuit composed of the depletion mode (p-)HEMTs
10
and
11
only, two power supplies are necessary thereby increasing the size of the module, which is a disadvantage when small-size and light-weighted wireless communication terminals are required. Therefore, in such occasions requiring light and miniature components such as in mobile communication terminals, it is necessary to adopt a device technology capable of fabricating a circuit that can be operated with a single power supply.
FIG
1
B is another example of a circuit diagram using a single power supply in order to overcome the disadvantage of FIG.
1
A.
Referring to
FIG. 1B
, this circuit uses a combination of a depletion mode (p-)HEMT
10
′ and an enhancement mode (p-)HEMT
11
′. However, monolithically integrating this circuit requires a device technology which can fabricate the depletion mode and enhancement mode (p-)HEMTs on a single substrate. In general, monolithic integration of the depletion and enhancement mode (p-)HEMTs can be embodied by adjusting the thickness of barrier layers.
FIG. 2
is a cross-sectional view illustrating a monolithically integrated E/D mode (p-)HEMT disclosed in the circuit diagram of FIG.
1
B.
Referring to
FIG. 2
, in order to fabricate a depletion mode (p-)HEMT, a gate pattern is formed using a photoresist, and then the ohmic layer
60
is etched selectively to expose the barrier layer
50
forming the exposed region
52
. In this case, the thickness of the barrier layer
50
is thick enough to produce a negative threshold voltage required for a depletion mode (p-)HEMT operation. Then, a gate electrode metal
56
is formed on the region
52
exposed by etching the ohmic layer
60
. Next, in order to form the enhancement mode (p-)HEMT, a gate pattern is formed by using the photoresist, and then an ohmic layer
60
is etched selectively to expose the barrier layer
50
. The exposed barrier layer is further etched to form the exposed region
54
. In this case, the thickness of the barrier layer
50
is thin enough to produce a positive threshold voltage required for a depletion mode (p-)HEMT operation. Then, a gate electrode metal
58
is formed on the exposed region
54
.
FIG. 3
is a graph illustrating the dependence of the threshold voltage on the thickness T of the barrier layer
50
shown in FIG.
2
. Referring to
FIG. 3
, as the thickness of the barrier layer
50
is increased, the threshold voltage becomes a negative value, and thus the (p-)HEMT operates in a depletion mode. On the contrary, as the thickness of the barrier layer
50
is decreased, the threshold voltage becomes a positive value, and thus the (p-)HEMT operates in an enhancement mode. Therefore, the E/D mode (p-)HEMT can be fabricated by adjusting the threshold voltage value, which can be implemented by controlling the thickness of the barrier layer
50
.
In order to enhance the uniformity of device characteristics and thus the yield of an integrated circuit, an epitaxial structure and a barrier layer etching technique that can maintain the thickness of the barrier layer
50
uniformly and accurately are required. In the conventional depletion mode (p-)HEMT structure, the uniformity of the threshold voltage can be ensured in a relatively easy fashion because the thickness of the barrier layer of the depletion mode (p-)HEMT can be adjusted accurately by the following reason. When the ohmic layer
60
is etched to expose the barrier layer
50
, it can be etched accurately by a selective wet etching or dry etching, since the ohmic layer subjected to etching is made of a material different from the barrier layer. However, in order to fabricate the enhancement mode (p-)HEMT the barrier layer made of the same material should be etched further to achieve a thin barrier layer required for a positive threshold voltage. Since the etching of the barrier layer is non-selective, accurate thickness control of the barrier layer is not easy and the thickness uniformity is poor, resulting in non-uniform threshold voltage. As a result, the yield of MMIC employing monolithically integrated E/D mode (p-)HEMTs is relatively low.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide a monolithically integrated E/D mode (p-)HEMT having a uniform threshold voltage by accurately adjusting the thickness of the barrier layer.
It is another object of the invention to provide a (p-)HEMT fabrication method suitable for obtaining the foregoing object.
To accomplish the above objects and other features, a monolithically integrated E/D mode (p-)HEMT structure is provided. The monolithically integrated E/D mode (p-)HEMT structure comprises: a buffer layer formed on a semi-insulating substrate; a channel layer formed on the buffer layer; a spacer layer formed on the channel layer; a first barrier layer, a second barrier layer, and a third barrier layer formed on the spacer layer in sequence; an ohmic layer formed on the third barrier layer; a first exposed gate region for a depletion mode (p-)HEMT formed by selective etching the ohmic layer such that the third barrier layer is exposed; a second exposed gate region an enhancement mode (p-)HEMT formed by selective etching the ohmic layer and the third barrier layer such that the second barrier layer is exposed; and gate electrodes respectively formed on the first exposed gate region and the second exposed gate region.
According to another aspect of the invention to accomplish the foregoing objects, a method for fabricating a monolithically integrated E/D mode HEMT is provided. The method comprises the steps of: forming a buffer layer, a channel layer, spacer layer, a first barrier layer, a second layer, a third layer, and an ohmic layer grown on a semi-insulating substrate in sequence; selectively etching the ohmic layer such that the third barrier layer is exposed to form a first exposed gate region; selectively etching the ohmic layer and the third barrier layer such that the second barrier is exposed to form a second exposed gate region; and forming gate electrodes on the first exposed gate region and the second exposed gate region, respectively.
Kwangju Institute of Science and Technology
Louie Wai-Sing
Marger & Johnson & McCollom, P.C.
Pham Long
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