Monolithically integrated data memory arrangement and method for

Details Monolithically integrated data memory arrangement and method for Monolithically integrated data memory arrangement and method for

1994-01-24

1995-03-07

Fears, Terrell W.

Static information storage and retrieval

Addressing

36518909, 36523006, G11C 1300

Patent

active

053964705

ABSTRACT:
In a memory arrangement and operating method therefor which enables an accelerated table search, an address generator, which operates according to a hash method, and an addressable memory are, integrated on a chip. A further advantage is achieved when the address generator is programmable, so that the hash method can be variably prescribed. A further acceleration is achieved when a CRC method is utilized for the calculation of the hash addresses and when intermediate results of the polynomial division are stored in tables. Two advantages are thus exploited. One advantage is an increase in speed due to the integration, and the further advantage is an increase in speed due to the accelerated polynomial division, as well as the high access hit rates inherent in the hash method.

REFERENCES:
patent: 4841487 (1989-06-01), Demura et al.
"Datenstrukturen und Datenorganisationen", Ollmert, H. J., Oldenbourg, 1989, pp. 133-162.

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