Patent
1977-08-08
1978-06-20
Wojciechowicz, Edward J.
357 23, 357 41, 357 42, H01L 2978
Patent
active
040965228
ABSTRACT:
A ROM with a matrix array of insulated gate enhancement type field effect transistors in each of which any information is not yet written is preliminarily prepared by a plurality of strip-shape diffusion regions doped at a predetermined interval in a given conductivity type semiconductor substrate and having a conductivity type opposite to that of the substrate, a plurality of strip-shape electroconductive metal layers formed through a first relatively thick insulation layer on the substrate at a predetermined interval so as to intersect the respective diffusion regions; and a plurality of gate electrode foils each formed through a second insulation layer thinner than the first insulation layer on that surface portion of the substrate which positions between the corresponding mutually facing ones of the diffusion regions so as integrally to project from the corresponding one of the electroconductive metal layers. An impression of information or absence thereof is controlled over the respective field effect transistors at the matrix intersections of the ROM by selectively implanting an impurity of the same conductivity type as that of the diffusion regions in the substrate through those exposed surface portions of the second insulation layer which are disposed between each of the gate electrode foils and the corresponding mutually facing ones of the diffusion regions, thereby providing an improved monolithic semiconductor mask programmable ROM and a method for manufacturing the same.
REFERENCES:
patent: 3959025 (1976-05-01), Polinsky
IBM Tech. Bul., vol. 15, No. 9, pp. 2919-2920, Feb. 1973, R. Knepper.
Manabe Kenshi
Suzuki Yasoji
Tokyo Shibaura Electric Co. Ltd.
Wojciechowicz Edward J.
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