Patent
1990-05-18
1991-02-19
Munson, Gene M.
357 24, 357 48, 357 89, H01L 2702, H01L 2704, H01L 2978
Patent
active
049948881
ABSTRACT:
A semiconductor device comprising a semiconductor chip formed of a substrate of a first conductivity type and an epitaxial layer of the first conductivity type formed on the substrate, a charge transfer device section formed in the epitaxial layer and driven by a given clock, and a preset region of a second conductivity type formed adjacent to the charge transfer device section in the semiconductor ship. The preset region includes a first layer of the second conductivity type formed in a boundary portion between the substrate and the epitaxial layer, a second layer of the second conductivity type formed on the first layer the epitaxial layer, and a third layer of the second conductivity type formed on the second layer in the epitaxial layer to reach the surface of the substrate. The maximum value of the second conductivity type impurity concentration of the third layer is set smaller than the maximum value of the second conductivity type impurity concentration of the first layer. A bipolar transistor section is formed in the third layer.
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Russell A. Martin, "Optimized Retrograde N-Well for 1-.mu. CMOS Technology", IEEE Journal of Solid-State Circuits, vol. 21, Apr. 1986, pp. 286-292.
Kihara Kazuo
Taguchi Minoru
Kabushiki Kaisha Toshiba
Munson Gene M.
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