Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-09-28
2003-01-28
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S506000, C257S528000
Reexamination Certificate
active
06512283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of forming high quality factor passive components on silicon substrates.
More specifically, the present invention relates to formation of an etch mask on a silicon substrate and use of the etch mask to provide a low dielectric constant platform in the silicon substrate.
In a further and more specific aspect, the present invention relates to formation of a robust, high quality dielectric layer in a silicon substrate that is compatible with formation of active components to provide RF circuitry on the silicon substrate.
In another aspect, the present invention relates to formation of platforms suitable for carrying high speed digital busses.
2. Prior Art
In operation of RF integrated circuits, it is necessary to provide frequency-selective circuitry for filtering signals, amplifying selected signals with respect to other, unwanted signals and for other kinds of RF functions. As frequencies increase, the provision of frequency-selective components becomes more problematic, especially in monolithic form.
Various kinds of frequency selection components have been developed over the years. Some of these, such as crystals and SAWs, depend on mechanical resonances to provide frequency selectivity. These types of devices tend to be incompatible with silicon circuitry requirements for reasons having to do with materials engineering and also because these types of devices require different, and much more expensive, packaging than is typical for silicon circuitry.
As a result, much work has focused on attempts to provide LC frequency selection functions on silicon. However, especially the inductors tend to be difficult to form with high quality factor, also known as “Q”. Additionally, the kinds of inductors that have been made tend to require large areas on the resulting integrated circuit. Some systems opt for separately-packaged frequency selection components, with the result that parts count is increased.
In an article entitled “Integrated Passive Components in MCM-Si Technology and their Applications in RF-Systems” by J. Hartung, 1998 Intl. Conf. on Multichip Modules and High Density Packaging, IEEE Cat. No. 0-7803-4850-8/98 (August '98), pp. 256-261, measured Qs and inductances for coils fabricated on silicon multichip modules are presented. In an article entitled “Applications for GaAs and Silicon Integrated Circuits in Next Generation Wireless Communication Systems” by L. M. Burns, IEEE JSSC, Vol. 30, No. 10, October 1996, pp.1088-1095, the demand for lightweight, portable communications products is addressed through monolithic integration of passive components in receivers and transmitters. These articles address system-level concerns that are met by combining separate circuits for the frequency selection functions.
Monolithic integration of inductors is also addressed in a variety of ways. For example, in an article entitled “Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's” by A. M. Niknejad and R. G. Meyer, IEEE JSSC Vol. 33, No. 10, October '98, pp. 1470-1481, design rules are discussed and performance tradeoffs are analyzed for spiral inductors.
In “A 1.8 GHz Low-Phase-Noise Spiral-LC CMOS VCO” by J. Craninckx and M. Steyaert, IEEE Cat. No. 0-7803-3339-X 96 (1996), pp. 30-31, silicon and GaAs technologies are discussed. Monolithic spiral inductors that are formed on conductive substrates tend to have reduced Qs due to losses that are caused by ground currents being induced in the substrate beneath the spiral inductors.
Unfortunately, while GaAs substrates may be made to be semi-insulating, thereby reducing or substantially eliminating parasitic substrate currents, GaAs substrates are expensive. Additionally, many GaAs devices have higher standby power requirements than do silicon devices.
Silicon substrates are typically provided with a lightly doped epitaxial layer for formation of active components (e.g., transistors and the like). A more heavily doped substrate is usually employed to support the epitaxial layer and to provide a low resistance ground return path for components formed in the epitaxial layer. Additionally, a highly doped substrate aids in prevention of latch-up phenomena.
While the heavily doped substrate provides a ground return path for the active circuits, it also results in reduced coil Q and losses when coils are formed on insulating layers above the substrate. As a result, silicon substrates that have been prepared for formation of active components are poorly suited to formation of high Q inductors.
One approach to providing monolithic inductors having increased Qs is to form a thick dielectric layer on the substrate. The inductors require a relatively thick dielectric layer in order to be adequately isolated from the conductive substrate. However, this results in a nonplanar surface, which interferes with photolithographic processes employed for definition of other circuit elements. Additionally, these dielectric layers tend to result in substantial stresses in the substrate, which can lead to bowing of the substrate and other problems.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide improvements in masking for formation of high quality, thick dielectric layers in silicon substrates.
Another object of the present invention is the provision of an improved platform for formation of high speed digital busses on silicon substrates.
An additional object of the instant invention is the provision of an improved method and apparatus for providing thick dielectric layers on silicon substrates while preserving planarity of the substrate surface.
Moreover, an object of the instant invention is the provision of an improved method and apparatus for providing reduction in coil losses while preserving capability for formation of active components on a silicon substrate.
Still a further additional object of the present invention is to provide an improved process for forming passive components on silicon.
Still another object of the present invention is the provision of a method, system and apparatus for suppressing losses in coils that are monolithically cointegrated with other microelectronic components.
Yet still another object of the instant invention is the provision of a method for forming thick, planar, low dielectric constant, low loss dielectric layers in silicon substrates.
And a further object of the invention is to provide a method, system and apparatus for suppressing losses in monolithic inductors.
And still a further object of the invention is the provision of method and apparatus, according to the foregoing, which is intended to improve operation of inductors in monolithic silicon circuits.
SUMMARY OF THE INVENTION
Briefly stated, to achieve the desired objects of the instant invention in accordance with an aspect thereof, provided is a dielectric platform having a dielectric constant that is reduced below that of silicon dioxide and that is formed in a silicon substrate. The dielectric platform may be formed to have a depth of up to tens of microns. The dielectric platform may be coplanar or nearly coplanar with a surface of a silicon wafer, promoting subsequent formation of active circuitry using conventional techniques. As a result, high Q inductors may be realized together with conventional CMOS, bipolar or BiCMOS structures to form monolithic RF circuits.
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Goltry Michael W.
Owens Douglas W.
Parsons Robert A.
Parsons & Goltry
Thomas Tom
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