Monolithic integration of silicon and gallium arsenide devices

Details Monolithic integration of silicon and gallium arsenide devices Monolithic integration of silicon and gallium arsenide devices

1986-06-13

1988-09-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

148DIG26, 148DIG72, 148DIG97, 148DIG149, 156610, 156612, 357 16, 357 41, 437 85, 437 90, 437 99, 437107, 437112, 437129, 437132, 437946, H01L 736, H01L 2120, H01L 21324

Patent

active

047742054

ABSTRACT:
Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO.sub.2 and Si.sub.3 N.sub.4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si.sub.3 N.sub.4 /SiO.sub.2 layers and final metallization is performed to complete the MOSFET fabrication. In an alternative embodiment, Si MOSFETs and aluminum gallium arsenide double heterostructure LEDs are formed in a similar manner.

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