Monolithic integrated circuit having compound semiconductor laye

Details Monolithic integrated circuit having compound semiconductor laye Monolithic integrated circuit having compound semiconductor laye

1990-12-11

1992-10-27

Jackson, Jr., Jerome

Superconductor technology: apparatus, material, process

High temperature , per se

Having tc greater than or equal to 150 k

357 4, 357 16, 357 61, 357 80, H01L 2702, H01L 2914

Patent

active

051594137

ABSTRACT:
A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.

REFERENCES:
patent: 3199003 (1965-08-01), Turner
patent: 3618203 (1971-11-01), Pryor
patent: 3721583 (1973-03-01), Blakeslee
patent: 3735211 (1973-05-01), Kapnias
patent: 3744120 (1973-07-01), Burgess et al.
patent: 3766634 (1973-10-01), Babcock et al.
patent: 3854892 (1974-12-01), Burgess et al.
patent: 3911553 (1975-10-01), Burgess et al.
patent: 3993411 (1976-11-01), Babcock et al.
patent: 3994430 (1976-11-01), Cusano et al.
patent: 4129243 (1978-12-01), Cusano et al.
patent: 4368098 (1983-01-01), Manasevit
patent: 4473938 (1984-10-01), Kobayashi et al.
patent: 4632712 (1986-12-01), Fan et al.
patent: 4833101 (1989-05-01), Fujii
patent: 4837536 (1989-06-01), Honjo
patent: 4855249 (1989-08-01), Akasaki
patent: 4908074 (1990-03-01), Hosoi et al.
patent: 4927471 (1990-05-01), Okuda
patent: 4948752 (1990-08-01), Geissberger et al.
patent: 4963508 (1990-10-01), Umeno
Ishiwara et al. Mat Res. Symp. Proced. vol. 67 1986 pp. 105-114.
Koren et al. Appl. Phys Lett (54)(11) Mar. 13, 1989 pp. 1054-1056 "Eppitaxial . . . Albation".
"A High Performance 0.12 .mu.m T-Shape Gate Ga.sub.0.5 In.sub.0.5 As/Al.sub.0.5 In.sub.0.5 As MOSFET Grown By MBE Lattices Mismatched on A GaAs Substrate", Y. K. Chen et al, IEDM 431-434 (Dec. 1986).
"0.1 -.mu.m Gate Al.sub.0.5 In.sub.0.5 As/GA.sub.0.5 In.sub.0.5 As MODFET Fabricated On GaAs Substrates", G. W. Wang et al, IEEE Trans Electron Devices 35(7) 818-823 (1988).
"New Ceramics Fill Performance Gaps", Ronald Pound, Electronic Packaging & Production, pp. 30-33, Sep. 1987.
"Heteroepitaxial Growth and Characterization of GaAs on Silicon-on-Sapphire and Sapphire Substrates", T. P. Humphreys et al, Appl. Phys. Lett. 54(17), Apr. 24, 1989, pp. 1687-1689.
"Heteroepitaxial Growth of GaAs on Sapphire Substrates By A Three-Step Method Using Low Pressure MOCVD" Sugimura et al, J. Crys. Growth, vol. 77, 1986, pp. 524-529.
"High Quality GaAs on Si and its Application to a Solar Cell", Ohmachi et al, Mat. Res. Soc. Symp. Proc., vol. 144, 1989, pp. 297-302.
"Epitaxy of GaAs on Si: MBE and OMCVD", Lee et al, Mat. Res. Soc. Symp. Proc., vol. 91, 1987, pp. 33-45.
"Lattice-Matched Epitaxial Growth of Semiconductor Films Onto Insulator (Mixed Fluoride)/Si Structures", Hiroshi Ishiwara et al, Japanese Jour. of Applied Physics, vol. 22 (1983), Supplement 22-1, pp. 201-204.

Affiliated with

Also associated with

Rating

Monolithic integrated circuit having compound semiconductor laye does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Monolithic integrated circuit having compound semiconductor laye, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Monolithic integrated circuit having compound semiconductor laye will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-909090