Patent
1986-02-28
1986-12-30
Munson, Gene M.
357 50, 357 55, 357 59, H01L 2702, H01L 2704, H01L 2906, H01L 2904
Patent
active
046332901
ABSTRACT:
Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
REFERENCES:
patent: 3861968 (1975-01-01), Magdo et al.
patent: 4209797 (1980-06-01), Egawa et al.
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4400411 (1983-08-01), Yuan et al.
patent: 4474624 (1984-10-01), Matthews
patent: 4477310 (1984-10-01), Park et al.
patent: 4554726 (1985-11-01), Hillenius
patent: 4558508 (1985-12-01), Kinney et al.
Degenkolb Eugene O.
Poppert Paul E.
Tabasky Marvin J.
GTE Laboratories Incorporated
Keay David M.
Munson Gene M.
LandOfFree
Monolithic CMOS integrated circuit structure with isolation groo does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Monolithic CMOS integrated circuit structure with isolation groo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Monolithic CMOS integrated circuit structure with isolation groo will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1551128