Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1998-02-09
2001-02-13
Fahmy, Wael (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C438S109000, C438S106000, C333S246000
Reexamination Certificate
active
06188128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a compact monoblock structure for stacked components.
2. Description of the Prior Art
A prior art multilayer circuit, described in U.S. Pat. No. 5,101,323, for example, is obtained by molding a plurality of layers, or levels, of components in a single, typically parallelepiped-shape block. Each layer of components includes at least one component and one track making a connection with the component and extending towards one side of the parallelepiped-shape block. Connections between levels, typically metallized tracks, are formed on the sides of the parallelepiped-shape block between the components of the various levels by etching the previously metallized block.
Because it is advantageous to use a single side of the block to carry the high-frequency or low-frequency component input and/or output connection points, this solution has the disadvantage of requiring the tracks to extend around one edge of the block. This implies technical problems including the difficulty of etching the track at the edge, the fact that the etching is more fragile at this edge, etc.
The invention aims to remedy this disadvantage by providing a monoblock structure for stacked components that does not require the tracks for making connections between the input and/or output connection points and the components to extend around an edge.
Another objective of the invention is to provide a process for fabricating a monoblock structure of the above kind.
SUMMARY OF THE INVENTION
To this end, the invention consists in a monoblock structure comprising at least two stacked component levels, each component level comprising:
a layer of insulative material forming a component and encapsulation storey,
at least one component, and
at least a first track a first end of which is connected to a connection point of the component,
the structure further comprising at least one second track disposed laterally and a first end of which is connected to a second end of the first track and printed circuit means forming a printed circuit storey and carrying at least one third track, a first end of the third track being coupled to a single input and/or output member one end of which is exposed on a face of the structure parallel to the component and printed circuit storeys and a second end of the third track being connected to a second end of the second track.
In a first variant, the signal input and/or output member is a pin member housed in a metallized hole in the printed circuit.
In another variant, the signal input and/or output member is a waveguide member carrying at least one grounding pin on one of its edges, the pin is housed in a metallized hole in the printed circuit means that forms one end of a grounding track and the first end of the third track is coupled to the waveguide.
The present invention also covers a process for fabricating a monoblock stacked component structure. The process comprises the steps of:
stacking at least two component levels, each component level comprising:
a layer of insulative material forming a component and encapsulation storey,
at least one component, and
at least one first track a first end of which is connected to a connection point of the component,
molding the at least two stacked component levels and printed circuit means forming part of a printed circuit storey and supporting at least one third track that is coupled to a signal input and/or output member upstanding orthogonally to the printed circuit means to form a monoblock structure preform,
cutting the monoblock structure preform to expose a section of the signal input and/or output member and an edge of the third track,
metallizing the resulting cut monoblock structure preform,
etching at least a second face of the metallized cut monoblock structure preform to form a second lateral track between a second end of the first track and a second end of the third track.
For fabricating a structure with pins, the process further comprises the steps of:
etching a first face of the metallized cut monoblock structure preform on which the section of the pin means is exposed to form a metallized area localized in the section, and
growing a bump on the metallized area.
The step of growing a bump on the metallized area is typically an electrolytic growth step.
REFERENCES:
patent: 3370203 (1968-02-01), Kravitz et al.
patent: 3746934 (1973-07-01), Stein
patent: 5291061 (1994-03-01), Ball
patent: 5294897 (1994-03-01), Notani et al.
patent: 5406125 (1995-04-01), Johnson et al.
patent: 5832598 (1998-11-01), Greenman et al.
patent: 5917388 (1999-06-01), Tronche et al.
patent: 5953588 (1999-09-01), Camien et al.
patent: 2688629A1 (1993-09-01), None
Heritage Dictionary of the English Lanuage, New College Edition, William Morris (Editor), p. 429, 1976.
Larcombe, et al., “Utilizing a Low Cost 3D Packaging Technology For Consumer Applications,” IEEE Transactions on Consumer Electronics, vol. 41, No. 4, pp. 1095-1101, Nov. 1995.
Alcatel
Fahmy Wael
Lee Hsien-Ming
Sughrue Mion Zinn Macpeak & Seas, PLLC
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