Monitored digital system

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371 57, G06F 1112

Patent

active

043205127

ABSTRACT:
A tester determines a system failure by employing an error detector (28, 30, 31; 40, 42, 44, 46) coupled to the plurality of output lines from a strobing circuit (10, 12, 14, 16, 18). This strobing circuit normally generates a singular signal on one of these plurality of lines. The error detector (28, 30, 32; 40, 42, 44, 46) responds to a singular signal being produced on two of the plurality of lines by producing an error signal. Thus, in the preferred embodiment a performance check can be performed on a significant number of internal digital lines by monitoring a single line which may be routed to an external connector.

REFERENCES:
patent: 2958072 (1960-10-01), Batley
patent: 3160852 (1964-12-01), Simms, Jr.
patent: 3371315 (1968-02-01), Huffman et al.
patent: 3693152 (1972-09-01), Hong
patent: 4087786 (1978-05-01), Lescinsky et al.
Sellers et al., Error Detecting Logic for Digital Computers, McGraw-Hill, 1968, pp. 59-63 and 212-219.

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