Monitor TEG test circuit

Details Monitor TEG test circuit Monitor TEG test circuit

1999-06-23

2001-05-29

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C714S733000

Reexamination Certificate

active

06239603

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test circuit for semiconductor devices and more specifically to a test circuit for a plurality of monitor TEGs (Test Element Groups) that monitors variations in process parameters in a semiconductor chip.
2. Discussion of the Background
With advances in manufacturing processes for miniaturization and high integration of semiconductor devices, reducing device parameter deviations within wafers and within chips due to process parameter variations has become an important problem in the improvement of semiconductor device manufacturing yields.
Conventionally, for process parameter monitoring, in-wafer TEGs (Test Element Groups), dicing line TEGs (TEGs in dicing line regions), and in-chip discrete element TEGs have been employed. However, they are insufficient as monitor TEGs for evaluating variations in process parameters for each chip. In view of monitoring process parameter variations within a chip, the demand has increased for a monitor TEG test circuit that allows process parameter variations to be evaluated with precision.
Here, the process parameter monitoring is to monitor deviations of characteristics of components of semiconductor devices from their design values due to variations in process parameters. The components to be monitored include discrete components, such as diffused resistors, diodes, transistors, etc., circuits, such as inverters, ring oscillators, etc., wiring TEGs each consisting of a group of contact holes and cross-over wirings, and so on.
The monitor TEGs are tested mainly in the middle of wafer processing in order to locate as early as possible faults due to variations in processing conditions. The wafer is diced into chips and the resultant chips are sealed in packages. After that, using an LSI tester good ones are selected out of packaged semiconductor devices and then shipped.
The causes of faults found after packaging are analyzed using an SEM (Scanning Electron Microscope) with the packages opened and then used to improve the manufacturing process. However, such a conventional destructive fault analysis method involves much time and effort. The fact is that effective feedback of fault data due to variations in wafer processing is considerably difficult.
That is, the main objective of the conventional monitor TEG-based intermediate testing in the wafer processing is to detect variations in the wafer processing as early as possible and contribute to the improvement of the manufacturing process.
SUMMARY OF THE INVENTION
Although, as described above, the conventional monitor TEG testing has been mainly intended to evaluate the effects of variations in process parameters within a wafer, among wafers, and among manufacturing lots, the advances in microstructuring and high-integration technology for semiconductor devices have increased the demand for monitor TEGs for evaluating variations in process parameters with precision and the development of a test circuit therefor in order to examine the effects of process variations within a chip.
The conventional monitor TEG testing can be carried out only in the middle of wafer processing. The monitor TEGs cannot be utilized for the shipment test after packaging, the reliability test, and the fault analysis for devices failed in the user site.
It is a first object of the present invention to provide monitor TEGs and a test circuit therefor which allow the effects of process parameter variations within a semiconductor chip to be evaluated with precision for an analysis of reductions in manufacturing yields of large-scale integration semiconductor devices.
It is a second object of the present invention to allow monitor TEG test results to be output with ease and at any point of time by forming monitor TEGs and a test circuit therefor on a semiconductor chip together with a semiconductor device and inputting test signals after package sealing (including plastic molding).
A monitor TEG test circuit of the present invention comprises a plurality of monitor TEGs for extracting the effects of process parameter variations placed in selected positions scattered in a chip and a circuit for selectively controlling the monitor TEGs, and selectively monitors the monitor TEGs by using test signals, thereby implementing process monitoring for process parameter variations.
In addition, the terminals for test signals are used in common with the external terminals of the semiconductor device by means of programmable enable signals, thereby keeping the external terminals from increasing for the testing purpose.
Specifically, the monitor TEG test circuit of the present invention is characterized by monitoring process parameter variations within a chip by forming the plurality of monitor TEGs and the semiconductor device on the same chip and selectively testing the monitor TEGs.
Preferably, the external terminals of the semiconductor device are programmably diverted by the test signals to input/output terminals of the monitor TEG test circuit.
According to an aspect of the present invention, there is provided a test circuit for n (n is an integer of more than one) number of monitor TEGs which are formed on the same chip as a semiconductor device is formed and placed in selected positions in the chip, wherein each of the monitor TEGs consists of a ring oscillator, and the test circuit comprising: a TEG control circuit responsive to externally applied test signals T
0
and T
1
to T
n
for outputting control signals G
1
to G
n
to control the number n of monitor TEGs, respectively; an n-input NOR gate or n-input OR gate responsive to outputs A
1
to A
n
of the monitor TEGs for outputting one of the outputs A
1
to A
n
Of the monitor TEGs; at least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T
0
and T
1
to T
n
; and a data output terminal of the semiconductor device which is diverted by an enable signal to an output terminal for the output of the n-input NOR or OR gate, the at least one data output terminal of the semiconductor device being connected to an input of the TEG control circuit, outputs of the TEG control circuit for outputting the control signals G
1
to G
n
being connected to the inputs of the monitor TEGs, respectively, and the output of the n-input NOR or OR gate being connected to the data output terminal of the semiconductor device.
Preferably, the ring oscillator has a two-input NOR gate to receive a corresponding one of the control signals G
1
to G
n
.
Preferably, the TEG control circuit comprises n number of two-input NAND gates each having its input connected to receive the test signal T
0
and its other input connected to receive a respective one of the test signals T
1
to T
n
and providing a respective one of the control signals G
1
to G
n
.
According to another aspect of the present invention, there is provided a test circuit for an n (n is an integer of more than one) number of monitor TEGs which are formed on the same chip as a semiconductor device is formed and placed in selected positions in the chip, wherein each of the monitor TEGs consists of a three-terminal elements having first, second and third terminals, and the test circuit comprising: a TEG control circuit responsive to externally applied test signals T
0
and T
1
to T
n
for outputting control signals G
1
to G
n
to control the n number of monitor TEGs, respectively; a first external terminal for inputting first input data to the semiconductor device via a buffer circuit; a second external terminal for inputting second input data to the semiconductor device via a buffer circuit; and at least one data output terminal of the semiconductor device which is diverted by an enable signal to an input terminal for one of the test signals T
0
and T
1
to T
n
, the at least one data output terminal of the semiconductor device being connected to an input of the TEG control circuit, the three-terminal element in each of the monitor TEGs having its first terminal c

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