Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Patent
1992-07-31
1994-07-12
Brier, Jeffery
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
345 3, G09G 512
Patent
active
053292901
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a monitor control circuit for driving a monitor which operates at a second pixel frequency on the basis of a digital image signal with a first pixel frequency.
As is generally known, computer monitors are driven by graphic cards of different categories depending on the requirements which have to be fulfilled with regard to the screen resolution demanded, said graphic cards differing from one another with respect to the horizontal and the vertical resolution, i.e., the number of pixels in the horizontal and in the vertical direction, as well as with respect to the pixel frequencies. Known graphic card standards are, for example, MDA (320.times.200 pixels, black-and-white, at 16 MHz pixel frequency), CGA (320.times.200 pixels, color, at 20 MHz pixel frequency), HERCULES (740.times.400 pixels, black-and-white, at 27 MHz pixel frequency), EGA (640.times.350 pixels, color, at 30 MHz pixel frequency), VGA (640.times.480 pixels, color, at 32 MHz pixel frequency), SUPER-EGA (800.times.600 and 1,024.times.768 pixels, respectively, color, at 50 MHz pixel frequency), and, recently, the so called HR (High Resolution) graphic systems with 1,024.times.768, 1,080 .times.1,024 as well as 1,600.times.1,280 pixels, color, at pixel frequencies between 60 MHz and 170 MHz. To the person skilled in the art it will be obvious that these various graphic standards differ also with regard to the line frequencies, i.e., the inverse of the horizontal synchronization signal periods, which occur at 17 kHz, 22 kHz, 25 kHz, 31.5 kHz, 50 kHz as well as 64 to 84 kHz in the case of the above-mentioned systems.
The wish to be capable of converting the output signals of the various graphic standards into screen images by means of a single monitor has existed for an extended period of time. For this purpose, so called "Multisync" monitors are used at present, such monitors being capable of operating at different horizontal synchronization signal frequencies by means of oscillating circuits which are adapted to be switched over. In view of the fact that the switching over of the "Multisync" monitor from one graphic standard to the next and, consequently, from one operating frequency to the next entails a certain transient recovery time, the switching over of the representation on the screen from one graphic standard to the next will cause interruptions of the screen display or initial image interference. It is self-evident that the complexity of a "Multisync" monitor will increase in proportion to the increase in the number of graphic card standards which can be dealt with by said monitor. The known "Multisync" monitors are also unable to display two segments, which are created by two different graphic cards, on one common screen.
DE-A1-38 04 460 discloses a monitor control circuit for driving a monitor which operates at a second pixel frequency on the basis of a digital image signal with a first pixel frequency, comprising an input-side serial-parallel converter in the form of a shift register whose output has connected thereto a video storage device wherein the input-side image signal can be stored after its serial-parallel conversion. In view of the fact that the storage device is only a shift register for serial-parallel conversion, which, for the purpose of carrying out serial-parallel conversion, is clocked with the clock of the subsystem after the respective appearance of the blank signal of the subsystem, the input-side signal is written into the video storage device at the frequency of its subsystem clock. Due to the lack of synchronism between the writing of the image signal into the video storage device with the first subsystem clock and the reading from the video storage device with the main system clock, there may be overlaps in writing and reading. According to the prior art, these overlaps are eliminated by not updating some image elements of each segment by giving the transfer cycle and, consequently, the reading of the video storage device priority over refreshing. The result of this type of con
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Cartwright Ian
Schwarz Stefan
Brier Jeffery
Dougherty Ralph H.
SPEA Software AG
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