Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-07-11
2004-03-30
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06714036
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to the testing of integrated circuits (ICs) and more particularly to monitor circuitry and a method for testing analog and/or mixed signal ICs.
BACKGROUND ART
Continuing increases in the complexity and density of analog and mixed signal integrated circuits (ICs) have imposed a challenge to the testing of circuitry within the circuits. A specific circuit design may exhibit a particular “signature” with respect to signal responses. While signature analysis has been successfully used to detect faults within digital ICs, the use of signature analysis for detecting faults within analog and mixed signal ICs is still in its infancy.
In current analog and mixed signal ICs testing techniques, the analog signals for testing are often distorted due to the need to transfer the signals to an off-chip environment. Test buses (e.g., IEEE 1149.4 standard), scan circuitry, oscilloscopes, and signal processing algorithms are often required, thereby adding to the problems encountered with parasitic loading and coupling.
One approach for testing analog and mixed signal ICs without the need to transfer the signals to the off-chip environment is to implement a built-in self-test (BIST) scheme. Since the analyses are performed on-chip, many of the problems associated with off-chip testings are eliminated. Brosa and Figueras in
Digital Signature Proposal for Mixed
-
Signal Circuits
, ITC International Test Conference, IEEE (2000), describe a system and method for testing mixed-signal ICs using a BIST scheme. According to the system, a zone detector is used to generate a control line that is swept across a Lissajous figure which is signatory of the IC. At each predefined period, a zero-crossing detector and counter counts the number of times the control line crosses the Lissajous figure. The number of crossings in the predefined period indicates the operational status of the IC. The zone detector for generating the control line consists of three operational amplifiers (op-amps) that are arranged in successive stages. One concern with the use of op-amps is the excessive area requirements of the op-amps, as compared to the IC under test, since each op-amp requires a significant amount of circuitry for implementation. Another concern is that the circuitry within the op-amps adds to the complexity and cost of manufacturing.
What is needed is a system and method for testing analog and mixed signal ICs, such that the size, complexity, and cost of manufacturing are reduced.
SUMMARY OF THE INVENTION
Monitor circuitry for identifying an operational status of a device under test (DUT) includes a comparison circuit and a sense amplifier. The comparison circuit comprises a set of control transistors and a set of sense transistors. The control transistors include control input terminals for receiving reference signals. The reference signals establish a testing condition that is characterized by a signal relationship between a first current flow and a second current flow. The sense transistors are operatively associated with the control transistors, such that biasing sense input terminals of the sense transistors with sampled signals received from the DUT varies the signal relationship between the first current flow and the second current flow. The variation in the signal relationship is accelerated by the sense amplifier. The variation in the signal relationship is indicative of the operational status of the DUT at the sampling instance of acquiring the sampled signals.
In one embodiment, the comparison circuit includes four transistors that are cooperatively arranged in a parallel configuration, including two control transistors and two sense transistors. A first conduction path for the first current flow is coupled to the source/drain regions of two of the four transistors. A second conduction path for the second current flow is coupled to the source/drain regions of the other two transistors. The first and second conduction paths are in parallel from the four transistors of the parallel configuration to the sense amplifier.
The parallel configuration may be arranged such that: (1) the two control transistors are connected to the first conduction path and the two sense transistors are connected to the second conduction path, (2) the two control transistors are connected to the second conduction path and the two sense transistors are connected to the first conduction path, and (3) one control transistor and one sense transistor are connected to the first conduction path while the other control transistor and the other sense transistor are connected to the second conduction path. Accordingly, each of the conduction paths may be coupled to the source/drain regions of: (1) two control transistors, (2) two sense transistors, or (3) one control transistor and one sense transistor.
Prior to testing, the monitor circuitry is initialized such that the first current flow at the first conduction path is equal to the second current flow at the second conduction path, if the two sampled signals satisfy a specific signal relationship condition. At a sampling instance, a set of reference signals is received at the control input terminals of the two control transistors. The reference signals may be constant voltages for controlling the current flows that are conducted through the two control transistors. The reference signals establish a testing condition with respect to the signal relationship between the first current flow and the second current flow. In an x-y plane, the reference signals are indicative of a boundary that divides two identifiable zones.
At a testing instance, a set of sampled signals are received at the sense input terminals of the two sense transistors. The sampled signals are analog signals which will determine the current flows that are conducted through the two sense transistors. The sampled signals vary the signal relationship between the first current flow and the second current flow. In the x-y plane, the sampled signals define a coordinate. The variation in the signal relationship indicates a location of the coordinate with respect to the boundary. In one testing scenario, the variation indicates whether the coordinate is on one side of the boundary because the first current flow is greater than the second current flow or on the other side of the boundary because the second current flow is greater than the first current flow.
The changes in the signal relationship between the first current flow and the second current flow are accelerated by the sense amplifier. The sense amplifier is configured to amplify a node voltage at a first node when the first current flow is greater than the second current flow or to amplify a node voltage at a second node when the second current flow is greater than the first current flow.
The monitor circuitry may also include output inverters. A first output inverter is coupled to the first node to invert the node voltage at the first node to provide a first digital output. A second output inverter is coupled to the second node to invert the node voltage at the second node to provide a second digital output. The first digital output and the second digital output are complementary digital outputs.
In accordance with the inventive method, a sequence of first and second digital outputs is generated using sequential sampled signals. Moreover, the reference signals may be adjusted to define other boundaries in the x-y plane. Subsequent downstream processing compares at least one of the first and second digital outputs with a corresponding predetermined reference digital signal to determine the operational status of the DUT.
An advantage of the invention is that the operational status of the DUT can be determined by a relatively simple device. This is potentially important, since the simplicity of the device reduces the hardware requirements needed for testing. Accordingly, the test status of the DUT is determined in a relatively short period of time. Moreover, the cost overhead for manufacturing is significantly reduced relative
Figueras Joan
Muradali Fidel
Agilent Technologie,s Inc.
Nguyen Tung X.
Nguyen Vinh P.
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