Molds for wafer scale molding of protective caps

Details Molds for wafer scale molding of protective caps Molds for wafer scale molding of protective caps

2002-01-09

2004-07-27

Mackey, James P. (Department: 1722)

Static molds

Container-type molding device

Of named component

C249S162000, C425S408000

Reexamination Certificate

active

06766998

ABSTRACT:

TECHNICAL FIELD
This invention relates to the molding and application of protective caps to microelectronic semiconductor chips on a wafer scale as opposed to application on an individual chip basis. More particularly the invention relates to the molds used to form the protective caps.
BACKGROUND ART
Semiconductor chips are normally packaged in a protective layer or layers to protect the chip and its wire bonds from atmospheric and mechanical damage. Existing packaging systems typically use epoxy molding and thermal curing to create a solid protective layer around the chip. This is normally carried out on individually diced chips bonded to lead frames and so must be done many times for each wafer. Alternative methods of packaging include hermetically sealed metal or ceramic packages, and array packages such as ball grid array (BGA) and pin grid array (PGA) packages. Recently wafer scale packaging (WSP) has started to be used. This is carried out at the wafer stage before the chips are separated. The use of molding and curing techniques subjects the wafer to both mechanical and thermal stresses. In addition the protective cap so formed is a solid piece of material and so cannot be used for MEMS devices, since the MEMS device would be rendered inoperable by the polymer material. Existing packaging systems for MEMS devices include thematically sealed packages for individual devices, or use silicon or glass wafer scale packaging, both of which are relatively high cost operation.
DISCLOSURE OF THE INVENTION
In one broad form the invention provides pair of molds formed substantially of silicon or silicon alloy for molding a sheet of thermoplastic material into an array of microstructures, each of the molds being a substantially planar wafer having a working face and rear face, the molds each having one or more micro fabricated recesses in their working faces which, when the working faces are placed face to face, define at least one cavity between the two molds, wherein the recesses on the molds are configured such that the molds only contact each other on the working faces, when the working faces are placed face to face.
In plan view the first mold may have at least one first recess in the respective working face for each cavity and the second mold may have at least one first groove in the respective working face for each cavity, such that when the two molds are in use, the at least one first recess defines a central portion of the cavity and the at least one groove defines a perimeter wall portion of the cavity extending from the edges of the central portion.
Preferably the at least one first recess is, in plan view, generally rectangular.
One of the molds may have a recess therein having a base and one or more pillars of mold material extending from the base to the plane of the working face.
One of the molds may have a recess therein having a base and wherein at least part of the base is concave or convex with respect to the respective mold's working face.
The other of the molds may have a second recess therein having a second base and part of the second base may be concave or convex with respect to the respective mold's working face.
When two molds are used with concave or convex portions, a lens shaped cavity may be defined.
The molds are preferably formed of a semiconductor material, such as silicon.
The working surfaces of the molds have preferably been prepared and the recesses have been formed using conventional lithography and deep silicon etching techniques.
In use, a spacer may be provided between the two molds such that the working faces of the molds do not contact each other.


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