Molded pin grid array package GPT

Electricity: electrical systems and devices – Miscellaneous

Patent

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Details

26427217, 29588, 174 52PE, H05K 706

Patent

active

046881522

ABSTRACT:
A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins. The other flat-faced mold platen contains molding cavities that are in registry with and slightly larger than the PW boards. The mold cavities include a series of ribs that are distributed around the cavity periphery. These ribs bear against the PW board when the mold is assembled so that the PW board is centered and pressed against the flat face of first platen in the region outboard of the pin-grid pattern. When a liquified plastic encapsulant is forced into the mold the cavities will be filled and the liquid will be excluded from the pin side of the PW board.

REFERENCES:
patent: 3701451 (1972-10-01), Schindler
patent: 4100566 (1978-07-01), Okikawa
patent: 4460537 (1984-07-01), Heinle
patent: 4631805 (1986-12-01), Olsen

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