Molded flip chip package

Details Molded flip chip package Molded flip chip package

2000-12-19

2003-10-14

Talbott, David L. (Department: 2827)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C438S125000, C438S126000, C438S127000

Reexamination Certificate

active

06632704

ABSTRACT:

COPYRIGHT NOTICE
Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of integrated circuit packaging. More particularly, the invention relates to an epoxy package that is formed in a single molding operation.
2. Description of the Related Art
Traditionally, semiconductor chips have been electrically coupled to electrical traces on a substrate via wire inter connects that are soldered on one end to the top active area of the chip and soldered to trace pads on the substrate that surround the chip on the other end. These types of interconnects are not particularly efficient, requiring space for both the surface area of the chip and a perimeter region for the trace pads, resulting in larger chip packages. To more efficiently utilize the substrate surface and facilitate smaller chip packages, the flip chip interconnection process was developed. Essentially, the active surface of the semiconductor chip is flipped over to face the substrate and the chip is soldered directly to trace pads located adjacent to the active surface. The result is a more compact and space-efficient package.
One of the most successful and effective methods of electrically connecting a flipped chip utilizes controlled-collapse chip connection technology (C4). First, solder bumps are applied to pads on the active side of the chip, the substrate or both. Next, the solder bumps are melted and permitted to flow, ensuring that the bumps are fully wetted to the corresponding pads on the chip or substrate. A tacky flux is typically applied to one or both of the surfaces to be joined. The flux-bearing surfaces of the chip and substrate are then placed in contact with each other in general alignment. A reflow is performed by heating the chip and substrate package to or above the solder's melting point. The solder on the chip and the substrate combine and the surface tension of the molten solder causes the corresponding pads to self-align with each other. The joined package is then cooled to solidify the solder. The resulting height of the solder interconnects is determined based on a balance between the surface tension of the molten solder columns and the weight of the chip. Any flux or flux residue is removed from the chip and substrate combination in a defluxing operation. Finally, an epoxy underfill is applied between the bottom surface of the chip and the top surface of the substrate, surrounding and supporting the solder columns. The reliability and fatigue resistance of the chip substrate solder connection is increased significantly. The underfill acts to carry a significant portion of the thermal loads induced by coefficient of thermal expansion (CTE) differences between the chip and substrate, rather than having all the thermal load transferred through the solder columns.
It is desirable in many integrated circuit applications to utilize as thin a substrate or film as possible to maximize the electrical performance of the resulting packaged chip. Typically, thin substrates or films are comprised of a polymeric material and are 0.05 to 0.5 mm thick. A thin substrate's shorter vias help reduce loop inductance within the substrate. Unfortunately, these thin substrates are very flexible making it difficult to attach solder balls or pins thereto. Furthermore, in unreinforced form they are susceptible to damage during installation and removal operations. The current practice is to bond rigid blocks of a suitable material to the periphery of the substrate to stiffen the entire package. The additional operation of bonding the rigid blocks to the thin substrate significantly increases the cost of the thin substrate package compared to a comparable package with a thicker substrate.
A typical prior art chip package utilizing a thin substrate is illustrated in
FIG. 1. A
silicon chip
110
is electrically coupled and joined to a thin substrate
120
by reflowed solder bumps
130
. The chip package may also include various passive components
140
, such as resistors and capacitors, also electrically coupled to the substrate
120
. An epoxy underfill
160
supplements the solder bump joint
130
between the chip
110
and the thin substrate
120
. A solder
145
may also be present around each of the passive components. Finally, stiffening blocks
150
comprising a suitable polymeric or ceramic or metal material are attached to the general periphery of the thin substrate
120
with an adhesive
155
to increase the overall rigidity of the package. Although not shown, the thin substrate may have attached to its backside a ball grid array (BGA) or pin grid array (PGA) to facilitate attachment of the chip package with a circuit board.


REFERENCES:
patent: 5450283 (1995-09-01), Lin et al.
patent: 5784261 (1998-07-01), Pedder
patent: 5895229 (1999-04-01), Carney et al.
patent: 5981314 (1999-11-01), Glenn et al.
patent: 5998243 (1999-12-01), Odashima et al.
patent: 6038136 (2000-03-01), Weber
patent: 6048483 (2000-04-01), Miyajima
patent: 6049122 (2000-04-01), Yoneda
patent: 6071755 (2000-06-01), Baba et al.
patent: 6081997 (2000-07-01), Chia et al.
patent: 6187243 (2001-02-01), Miyajima
patent: 6344162 (2002-02-01), Miyajima
patent: 0971401 (2000-01-01), None
patent: 2297652 (1996-07-01), None
patent: 59-208756 (1984-11-01), None
patent: 11-195742 (1999-07-01), None
patent: P2000-150760 (2000-05-01), None
PCT Search Report, PCT/US02/117882, Oct. 22, 2002.

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