Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-03-30
2002-11-26
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S737000, C257S778000, C257S774000, C257S712000, C257S704000, C257S710000, C257S698000, C257S696000, C257S706000, C257S707000, C257S726000, C257S718000, C257S719000, C257S675000, C257S720000, C257S787000, C361S717000, C361S688000
Reexamination Certificate
active
06486554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to electronic packages and methods of forming thereof, and in particular pertains to an electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages.
In essence, a particular type of electronic package which consists of a PBGA (plastic ball grid array) package, and which is applicable to chip-scale or near-chip-scale applications, and is essentially constituted of a chip mounted on an organic, wire carrier or circuitized substrate the size of which may extend beyond the peripheral dimensions of the semiconductor chip. The foregoing relates to both wire-bond and flip chip packages and wherein in order to protect the semiconductor chip from the deleterious or debilitating effects of the environment, it is generally desirable to form an insulating body about the chip, this body generally being in the form of a molded epoxy material forming an encapsulant. Generally, as is well known in the technology, interfacial stresses which are generated between the encapsulating molded material, such as the epoxy which may be a thermoset plastic resin, and the circuitized substrate or chip carrier, can be quite considerable in magnitude and may result in delamination of the components as a result of exposure to moisture or during thermal cycling. This will adversely affect the reliability and possibly even completely destroy the electrical interconnections of the electronic package and the functional integrity thereof, leading to potentially extensive financial and economic losses. Heretofore, when applying the molded material producing the protective structure encompassing the semiconductor chip and forming the physical bond with the carrier or circuitized substrate on which the chip is positioned, the molded material has been confined to engagement with the surface on the side of the carrier or substrate on which the semiconductor chip is mounted, whereby the opposite or distal side of the carrier, on which there is normally disposed an array of solder balls (BGA's) is left unencapsulated so as to provide electrical connecting access for the solder balls. Although the encapsulation of the semiconductor chip and the resulting bonding with the circuitized substrate or carrier is effected by a molded compound generally constituted of an epoxy, the tendency in industry, at this time has been a shifting towards the use of mold compounds or bodies forming the encapsulate for the electronic package which has a lower coefficient of thermal expansion (CTE) than heretofore, whereby the interfacial stresses which extend normal to the surface of the carrier or circuitized substrate facing towards the semiconductor chip are reduced in the region extending about the periphery of the semiconductor chip. This, in essence, increases the bending of the electronic semiconductor chip-mounting package and decreases the fatigue life expectancy of the ball grid arrays (BGA). Although the stresses which are generated as a result of bending are ordinarily not a problem to the degree in chip-scale packages as they would be in larger PBGA's, these stresses must be still minimized due to the effect on BGA fatigue and to enable an increase in their length of service life. The fatigue life of such BGA's represents a particular problem for chip-scale packages, inasmuch as the solder ball size and the pitch between balls must be decreased in order to be able to provide sufficient numbers of interconnections with the small package size, whereby both of these decreases in pitch and size result in a shorter fatigue life for the structure.
Although the prior art has addressed itself to this problem by providing various improved bonding interconnections between the mold compound or material encapsulating a semiconductor chip and by also concurrently encapsulating the surface and, as required, potentially the peripheral side surfaces of the carrier or circuitized substrate, problems are still encountered in providing an adequate degree of adhesion between the components which will prevent delamination under conditions of bending or thermal cycling This problem has been addressed to some extent in co-pending U.S. patent application Ser. No. 09/430,075, (Attorneys Docket EN998109), in which there are disclosed various embodiments directed to the encapsulation of semiconductor chips or electronic packages with a mold material, such as a thermoset plastic or molded epoxy resin, and wherein the encapsultaing material also encompasses the periphery of the chip-mounting substrate or circuitized carrier and the surface thereof which faces towards the mounted semiconductor chip.
2. Discussion of the Prior Art
A number of publications are disclosed in the technology which concern themselves with the use of an encapsulating material extending about and bonding semiconductor chips to diverse kinds of circuitized substrates or carriers.
Thus, Hiruta U.S. Pat. No. 5,998,861 discloses a semiconductor device with a ball grid array (BGA) wherein an epoxy material provides an encapsulant between a semiconductor chip and the facing surface of a carrier for the ball grid array.
Odashima, et al. U.S. Pat. No. 5,998,243 discloses a method for the manufacturing of semiconductor devices and an apparatus, whereby a resin material forms an encapsulate between a semiconductor chip and a carrier on which the chip is mounted.
Yamada, et al. U.S. Pat. No. 5,864,178 discloses a semiconductor device with an encapsulating material constituting of a curable resin for bonding a flip-chip bonded semiconductor chip to the facing surface structure of a substrate or circuitized carrier body mounting the chip.
Other publications which concern themselves to some extent with various encapsulating materials adapted to be employed in electronic packages are Wang et al., U.S. Pat. No. 5,817,545; Thompson et al., U.S. Pat. No. 5,218,234, and Banerji et al., U.S. Pat. No. 5,203,076.
Although the foregoing publications each deal in different measures or degrees with various aspects in providing apparatus and methods for encapsulating semiconductor chips in order to protect the components of the electronic package against potentially deleterious environmental influences, and by utilizing various suitable encapsulating resins or thermosetting plastic materials, such as molded epoxy compounds or silicones, all of these publications limit the encapsulating interconnections or bonding between the circuitized semiconductor chip and the carrier or substrate in that the adhesion or bonding is only effected between the semiconductor chip and the surface of the substrate facing towards the superimposed semiconductor chip, and, at times as required, extending about the peripheral sides or edges of the substrate.
SUMMARY OF THE INVENTION
Accordingly, in order to significantly improve upon the foregoing methods and structure for adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, the present invention provides for a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip, which will counteract any tendency towards delamination between the components of the electronic package, in effect, between the semiconductor chip and the circuitized substrate or carrier; and considerably reduce stresses and strains so as to preserve the reliability of the electronic package.
In particular, in the utilization of transfer molding when encapsulating a semico
International Business Machines - Corporation
Williams Alexander O.
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