Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1998-03-02
2001-08-28
Hjerpe, Richard A. (Department: 2776)
Computer graphics processing and selective visual display system
Display driving control circuitry
C348S806000, C358S296000, C315S370000, C345S213000
Reexamination Certificate
active
06281889
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a circuit for reduction, typically referred to as cancellation, of Moiré effects.
BACKGROUND OF THE INVENTION
Moiré effects occur in displays due to interference between images and are particularly noticeable in pixelated image displays such as conventional cathode ray tube (CRT) displays. Moiré cancellation is a key feature of high-end display monitors (e.g., for computer CRT displays having a diagonal screen size of 17″ and above).
For such high-end monitors, auto speed tracking and programmable delay time for Moiré cancellation is becoming a demand because of the increasing number of video resolution modes which causes CRT speed to vary in a wide range.
Moiré cancellation is typically implemented in an analogue circuit in the time base integrated circuit (IC) of a display system, and it is known for such analogue Moiré cancellation circuitry to incorporate auto speed tracking and programmable delay time.
Moiré cancellation can alternatively be implemented in a simple digital circuit outside the time base IC if the IC does not provide such a feature, but the analogue techniques for auto speed tracking and programmable delay time would be very difficult to implement in such digital circuitry since the technologies of the analogue and digital circuits are so dissimilar. In conventional digital approaches, Moiré cancellation is typically implemented with a fixed delay time.
It is an object of the present invention to provide a Moiré cancellation circuit which uses a digital approach, which can be incorporated in a digital Time Base integrated circuit, and which can provide auto speed tracking and programmable delay time.
It is an object of this invention to provide a Moiré cancellation circuit which uses a digital approach, which can be incorporated in a digital Time Base integrated circuit, and in which the above disadvantages may be overcome or at least alleviated.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a Moiré cancellation circuit as claimed in claim
1
.
REFERENCES:
patent: 4599655 (1986-07-01), Hinn
patent: 5107188 (1992-04-01), Rindal
patent: 5440353 (1995-08-01), Yamazaki et al.
Hjerpe Richard A.
Motorola Inc.
Nguyen Kevin M.
Parker Lanny L.
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