Modulo reduction method using a precomputed table

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G06F 700

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055724540

ABSTRACT:
A modulo reduction method using a precomputed table to increase a reduction speed during the execution of ordinary operational processes using computers and comprises a first step which searches out with an index of an upper log.sub.2 t (t.gtoreq.1) bit number and adds the value stored in a table to a lower n(n.gtoreq.512) bit number; a second step, which if the result, obtained from the addition of said lower n bit number to the number searched out from the table at said first step, produces an overflow (1 bit), eliminates said overflow and finishes the execution of an operation; and a third step, which if said overlow does not occur at said second step, adds .sub.N on a modulo N to the result obtained from said first step and finishes the execution of the operation.

REFERENCES:
patent: 4742479 (1988-05-01), Kloker et al.
patent: 4870681 (1989-09-01), Sediak
patent: 4891781 (1990-01-01), Omura
patent: 5210710 (1993-05-01), Omura
patent: 5249148 (1993-09-01), Catherwood et al.

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