Modulo arithmetic unit having arbitrary offset and modulo values

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G06F 772

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047424796

ABSTRACT:
A modulo arithmetic unit for providing a sum or difference of two numbers of arbitrary value in a selected one of a plurality of moduli is provided. Each modulus has a lower and an upper boundary and a range of intermediate values. First and second adders are provided for respectively providing first and second outputs which respectively represent outputs compensated for and not compensated for a possible wraparound of the upper or lower boundary. Control circuitry is used to detect whether a wraparound occurred during the calculation depending upon the value of selective interstage carry signals of the first and second adders. The correct output is provided as a selected one of the outputs of the first and second adders in response to the control circuitry.

REFERENCES:
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patent: 4598266 (1986-07-01), Bernardson
"DSP Microprocessor ADSP-2100" Analog Devices Inc., Aug. 1986, pp. 1-35.
Roesgen et al., "Moving Memory Off Chip, DSP .mu.P Squeezes in More Computational Power" Electronic Design, Feb. 20, 1986, pp. 131-140.
Garde et al., "16-Bit-Slice Family Creates Ultrafast Digital Signal Processors" Electronic Design, May 17, 1984, pp. 136-144.
Raminarayar, "Practical Realisation of Mod p,p Prime Multiplier" Electronics Letters, Jun. 5, 1980, vol. 16, No. 2, pp. 466-467.

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